Samsung Electronics Co., Ltd.

Guk-Hyon Yon

Sangjin Hyun

Jae-young Ahn

Dong-Chul Yoo

Hun-hyeong Lim

Jeon-Il Lee

Young-jin Noh

Kwang-Min Park

Ji-Sang Yahng

Yu Gyun Shin

Ju-Mi Yun

Young-Seon Son

Gyoung Ho Buh

Joong-Yun Ra

Jung-Hwan Kim

Sunggil Kim

Jung-Geun Jee

Jeong-lim Nam

HongSuk Kim

Won-Jin Kim

Hunhyeong Lim

Sang-Yub Ie

Chang-Seob Kim

An ALD apparatus includes a first process chamber configured to supply a first source gas and induce adsorption of a first material film. A second process chamber is configured to supply a second source gas and induce adsorption of a second material film. A third process chamber is configured to supply a third source gas and induce absorption of a third material film. A surface treatment chamber is configured to perform a surface treatment process on each of the first to third material films and remove a reaction by-product. A heat treatment chamber is configured to perform a heat treatment process on the substrate on which the first to third material films are adsorbed in a predetermined order and transform the first to third material films into a single compound thin film.

Apparatus for atomic layer deposition and method of forming thin film using the apparatus

A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

Semiconductor devices and methods of manufacturing the same

Non-volatile semiconductor devices

Methods of manufacturing a semiconductor device are provided. The method includes forming a poly-silicon layer doped with first p-type dopants on a substrate, etching the poly-silicon layer and the substrate to form a poly-silicon pattern and a trench, forming device isolation pattern covering a lower sidewall of the poly-silicon pattern in the trench, thermally treating the poly-silicon pattern in a gas including second p-type dopants, forming a dielectric layer and a conductive layer on the thermally treated poly-silicon pattern and the device isolation pattern, etching the conductive layer, the dielectric layer, and the thermally treated poly-silicon pattern to form a control gate, a dielectric pattern, and a floating gate respectively.

Semiconductor device and method of manufacturing the same

A memory device includes a charge trapping layer on a substrate, an insulating layer on the substrate adjacent to the charge trapping layer and exposing an upper surface of the charge trapping layer, a dielectric layer on the exposed charge trapping layer and on the insulating layer, and an electrode on the dielectric layer, the electrode corresponding to the charge trapping layer.

Charge trapping type semiconductor memory device and method of manufacturing the same

A method of selectively heating a predetermined region of a semiconductor substrate includes providing a semiconductor substrate, selectively focusing a free carrier generation light on only a predetermined region of the semiconductor substrate, irradiating the free carrier generation light on the predetermined region of the semiconductor substrate to increase a free carrier concentration within the predetermined region of the semiconductor substrate, wherein the free carrier generation light causes the predetermined region to increase in temperature by less than a temperature necessary to change the solid phase of the predetermined region, and irradiating the semiconductor substrate with a heating light to selectively heat the predetermined region of the semiconductor substrate.

Method of increasing a free carrier concentration in a semiconductor substrate

Growing community of inventors

Hwaseong-si, South Korea

Guk-Hyon Yon