Intel Corporation

Guillermo Savransky

Jacob Doweck

Evgeni Krimer

Idan Mondjak

Ronny Ronen

Zeev Sperber

Efraim Rotem

Ittai Anati

Tsvika Kurts

Antonio Gonzalez

Doron Orenstien

Oren Lamdan

Geeyarpuram N Santhanakrishnan

Sagi Lahav

Daniel Skaba

Nicolas Worms

Eilon Hazan

Jason Ratner

Sharon Elmosnino

A memory access management technique is disclosed, one embodiment of which relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address. A processor may include load buffer entries having predictor table entries associated therewith, including saturation counters to record history of previous conflicts between loads and stores corresponding to the same target address. A watchdog unit may disable memory disambiguation (MD) if the MD causes too high a misprediction rate for load operation and store operation conflicts. In one embodiment, the MD is disabled if a flush counter value reaches a threshold.

Memory disambiguation techniques using counter ratio to selectively disable load/store conflict prediction

Counter-based memory disambiguation techniques for selectively predicting load/store conflicts

A high integration integrated circuit may comprise a plurality of processing cores, a graphics processing unit, and an uncore area coupled to an interface structure such as a ring structure. A generic debug external connection (GDXC) logic may be provisioned proximate to the end point of the ring structure. The GDXC logic may receive internal signals occurring in the uncore area, within the ring structure and on the interfaces provisioned between the plurality of cores and the ring structure. The GDXC logic may comprise a qualifier to selectively control the entry of the packets comprising information of the internal signals into the queue. The GDXC logic may then transfer the packets stored in the queues to a port provisioned on the surface of the integrated circuit packaging to provide an external interface to the analysis tools.

Generic debug external connection (GDXC) for high integration integrated circuits

Briefly, a processor and a method of estimating an active energy consumption of two or more cores of a processor based on dispatching micro operations to one or more execution units of the processor.

Method and apparatus to estimate energy consumed by central processing unit core

Memory access management techniques are described. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address. In an embodiment, a load operation may be predicted to not conflict with older pending store operations if a saturation counter corresponding to the load operation is below a threshold value and a maximum rate of mispredictions has not occurred. Other embodiments are also disclosed.

Devices, systems, and methods may perform micro-operation processing with data validity tracking to determine fast or slow mode processing at a reservation station. A method includes determining whether a condition related to validity of data in a reorder buffer of an out-of-order subsystem of a processor core is met, based on a criterion other than a valid data indication from said reorder buffer. In one embodiment, in a fast mode a reservation station may dispatch micro-operations to execution and in a slow mode the reservation station may wait for a valid indication from the reorder buffer prior to dispatching the micro-operation.

Method for data validity tracking to determine fast or slow mode processing at a reservation station

A partial execution unit of a splittable execution unit performs an operation on a portion of one or more arguments of a micro-operation to generate a first partial execution result of the micro-operation. A complementary portion of one of the arguments is passed through a bypass execution unit instead of through the splittable execution unit to generate a second partial execution result of the micro-operation. The first partial execution result and second partial execution result are concatenated into a full execution result.

Apparatus and methods for utilization of splittable execution units of a processor

A processor system and method that reduces the number of register value copying made from alias registers to corresponding real (architectural) registers. One method entails not performing an alias register to real register copying if the incoming instruction does not designate a real register. Another method entails delaying alias register to real register copying until the corresponding reorder buffer (ROB) entry is actually written to. Yet another method entails not performing an alias register to real register copying if the ROB entry is the same as the existing ROB entry. And, still another method entails further delaying or stalling the allocation of an ROB entry.

System and method of reducing the number of copies from alias registers to real registers in the commitment of instructions

A processor system and method that reduces the number of register value copying made from alias registers to corresponding real (architectural) registers. The method entails determining whether to copy the register value generated by executing an instruction from the alias register to the real register at the time the reorder buffer entry associated with the alias register is needed for a new instruction. If before the reorder buffer is needed for a new instruction, an interim instruction resulted in a new register value for the real register, then the original register value would be invalid at the time the reorder buffer entry is needed for the new instruction. Thus, there would not be a need to copy the original register value to the real register. The reduction in copying can make the processor system consume less power.

Growing community of inventors

Haifa, Israel

Guillermo Savransky