Synopsys, Inc.

Guillermo R Maturana

Arturo Salz

Dhiraj Goswami

Ngai Ngai William Hung

Jasvinder Singh

Qiang Qiang

Joseph T Buck

In-Ho Moon

Lisa R McIlwain

Alok Kuchlous

Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. A constraint solver can receive a set of constraints that is expected to cause performance problems when the system assigns random values to the set of random variables in a manner that satisfies the set of constraints. For example, modulo constraints and bit-slice constraints can cause the system to perform excessive backtracking when the system attempts to assign random values to the set of random variables in a manner that satisfies the set of constraints. The system can rewrite the set of constraints to obtain a new set of constraints that is expected to reduce and/or avoid the performance problems. The system can then assign random values to the set of random variables based on the new set of constraints.

Optimizing constraint solving by rewriting at least one bit-slice constraint

Optimizing constraint solving by rewriting at least one modulo constraint

Methods and apparatuses are described for reducing or eliminating X-pessimism in gate-level simulation and/or formal verification. A system can identify a set of reconvergent inputs of a combinational block in a gate-level design. Next, the system can determine whether or not the combinational block is expected to exhibit X-pessimism during gate-level simulation. If the combinational block is expected to exhibit X-pessimism during gate-level simulation, the system can modify the gate-level design to reduce X-pessimism during gate-level simulation. In some embodiments, the system can build a model for the gate-level design by using unique free input variables to represent sources of indeterminate values. The system can then use the model to perform formal verification.

Reducing x-pessimism in gate-level simulation and verification

One embodiment of the present invention provides a system that simulates behavioral constructs of a register transfer level design using indeterminate values. The system may receive hardware description language code which includes a construct that behaves differently depending on the value of an expression, e.g., the construct may execute different portions of code based on the value of a control expression, or it may store data in different storage locations based on the value of an index expression, etc. In response to determining that the expression's value is indeterminate, the system can execute two or more alternatives that are controlled by the expression, and then merge the results in some prescribed way. An embodiment of the present invention can enable a user to reduce the discrepancy between the results generated by a register transfer level simulation and the results generated by the associated gate level simulation.

Method and apparatus for simulating behavioral constructs using indeterminate values

One embodiment of the present invention provides a system that reuses information associated with a constraint solving operation for a problem domain. This system begins by receiving a constraint problem from the problem domain. Then, the system searches through a problem cache for an entry which corresponds to the canonical representation. If a corresponding entry does not exist in the problem cache, the system produces an entry in the problem cache for the canonical representation. Otherwise, if a corresponding entry already exists in the problem cache, the system generates a solution to the canonical representation by reusing the solver heuristic associated with the corresponding entry in the problem cache.

Enhancing performance of a constraint solver across individual processes

One embodiment of the invention provides a system that facilitates integrating a simulation log into a verification environment. The system operates by first creating the simulation log during a simulation of a register transfer language description of an integrated circuit design. Next, for each entry in the simulation log, the system places a corresponding entry in a 'log entry table.' When a user selects an entry from the simulation log, the system determines a file offset for the entry within the simulation log. Next, the system locates the corresponding entry in the log entry table. The system then uses the log entry table to locate entries within simulator state files, which describe which portion of the integrated circuit is being simulated. This enables the system to display the corresponding entries from the simulator state files to a user.

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Berkeley, CA, United States of America

Guillermo R Maturana