Other

Nvidia Corporation

Transmeta Corporation

Intellectual Ventures Holding 81 LLC

Institute for the Development of Emerging Architectures, L.l.c.

Vmware, Inc.

Facebook, Inc.

Datera, Inc.

Guillermo Juan Rozas

Alexander Klaiber

H Peter Anvin

David A Dunn

Paul S Serris

John P Banning

Ross Segelken

Alex Klaiber

Magnus Ekman

James Van Zoeren

Darrell D Boggs

Linus Torvalds

Jason Burke Wilson

Andrew M Shaw

Hens Vanderschoot

Brad Hoyt

Sridharan Ramakrishnan

Robert Paul Masleid

Lacky V Shah

Robert Bedichek

Parag Gupta

Richard Johnson

Godfrey P D'Souza

William Schnaitter

Robert F Cmelik

Charles R Price

Alan Hersh Karp

Lawrence Spracklen

John R Nickolls

Michael J Morrison

Roger A Golliver

Jerome C Huck

Robert Steven Glanville

Glenn T Colon-Bonet

Gautam B Doshi

Peter Markstein

Anurag Chaudhary

Richard Craig Johnson

Ben Hertzberg

Nickolas Andrew Fortino

Rohit Kumar

Brett Coon

Yusuf Cagatay Tekmen

Bruce Holmer

Eric Hao

Nathan Daniel Tuck

Brian Holscher

Scott Pitkethly

Madhu Swarna

Rupert Brauch

Chi Keung Lee

Aravindh Baktha

Jason Golbus

Michael Neilly

Thomas Kistler

Nathan Laredo

Samuel Charles Tsen, Jr

Sean Benton Franey

Gokul Govindu

David Hass

Bharath Krishnan

Robert Bedicheck

Nikhita Kunati

Daniel H Nelsen

David Dobrikin

Polychronis Xekalakis

Michael P Cornaby

A first thread is executed in a first pipeline of a first core of an integrated circuit (IC). The first core includes a first set of hardware structures. A second thread is executed in a second pipeline of a second core of the IC. The second core includes a second set of hardware structures. In response to a command to operate the IC with a unified core, the first core is combined with the second core to obtain the unified core. To unify the first core, the first pipeline is unified with the second pipeline to obtain a unified pipeline, and the first set of hardware structures is unified with the second set of hardware structures to obtain a unified set of hardware structures. A single thread is executed in the unified pipeline of the unified core using the unified set of hardware structures.

Dynamic reconfiguration of a multi-core processor to a unified core

A method for performing a write operation in a distributed storage system is disclosed. The method comprises receiving a first time-stamped write request from a proxy server. Further, the method comprises determining if the first time-stamped write request is within a time window of a reorder buffer and if the first time-stamped write request overlaps with a second time-stamped write request in the reorder buffer. Responsive to a determination that the first time-stamped write request is outside the time window or that the first time-stamped write request is within the time window but has an older time-stamp than the second time-stamped write request, the method comprises rejecting the first time-stamped write request. Otherwise, the method comprises inserting the first time-stamped write request in the reorder buffer in timestamp order and transmitting an accept to the proxy server.

Ordinary write in distributed system maintaining data storage integrity

Future write in distributed system maintaining data storage integrity

A coherence decoupling buffer. In accordance with a first embodiment, a coherence decoupling buffer is for storing tag information of cache lines evicted from a plurality of cache memories. A coherence decoupling buffer may be free of value information of the plurality of cache memories. A coherence decoupling buffer may also be combined with a coherence memory.

Coherence de-coupling buffer

Disclosed are a method and device in a network for utilizing larger block sizes for a logical disk, and further decomposing into smaller physical block sizes for a redundant encoding by utilizing an erasure coding logic to avoid a read&#x25a1;modify&#x25a1;write operation on a plurality of write operations. The device includes a receiving module, an encoding module, and a transmitting module. The receiving module configured to obtain a read request or a write request of a large block size to a storage unit over a network. In an embodiment, the storage unit comprising a plurality of physical devices of a smaller blocks size that is a divisor of the large block size. The encoding module to encode the received requests redundantly to persist media failures by reconstructing the requests on reads using the redundancy. The transmitting module transmits either a request command to initiate a read operation or an acknowledgment data on completion of a write operation.

System and method to utilize larger block sizes for logical disk and further decompose into smaller physical block sizes for redundant encoding by utilizing erasure coding

A dual-domain dynamic multiplexer and a method of transitioning between asynchronous voltage and frequency domains. One embodiment of the dual-domain dynamic multiplexer includes: (1) a first domain having a first voltage and a first clock, and a second domain having a second voltage and a second clock, (2) a plurality of data and data select input pairs wherein a data input of an input pair is in the first domain and a data select input of an input pair is in the second domain, and (3) a pre-charge stage in the second domain that is energized upon an edge of the second clock, whereby one data and data input pair is enabled and data latched in the second domain upon another edge of the second clock.

Dual-domain dynamic multiplexer and method of transitioning between asynchronous voltage and frequency domains

The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode.

Profiling code portions to generate translations

A method for detecting an instruction ordering violation in a CPU. The method includes receiving a reordered stream of instructions and detecting whether an ordering violation has occurred by using virtual addresses. The method further includes transferring results of the reordered stream of instructions from a load store buffer into a cache and detecting whether an ordering violation has occurred by using physical addresses. Subsequently, a recovery is initiated upon detection of an ordering violation.

Virtual address based memory reordering

A method for increasing the speed of execution by a processor including the steps of selecting a sequence of instructions to optimize, optimizing the sequence of instructions, creating a duplicate of instructions from the sequence of instructions which has been selected to optimize, executing the optimized sequence of instructions, and responding to an error during the execution of the optimized sequence of instructions by rolling back to the duplicate of instructions from the sequence of instructions.

Method for increasing the speed of speculative execution

Embodiments related to managing lazy runahead operations at a microprocessor are disclosed. For example, an embodiment of a method for operating a microprocessor described herein includes identifying a primary condition that triggers an unresolved state of the microprocessor. The example method also includes identifying a forcing condition that compels resolution of the unresolved state. The example method also includes, in response to identification of the forcing condition, causing the microprocessor to enter a runahead mode.

Lazy runahead operation for a microprocessor

Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic, and scheduler logic for scheduling the retrieved instruction for execution. The example scheduler logic includes a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.

Checkpointed buffer for re-entry from runahead

Systems and methods for coherency maintenance are presented. The systems and methods include utilization of multiple information state tracking approaches or protocols at different memory or storage levels. In one embodiment, a first coherency maintenance approach (e.g., similar to a MESI protocol, etc.) can be implemented at one storage level while a second coherency maintenance approach (e.g., similar to a MOESI protocol, etc.) can be implemented at another storage level. Information at a particular storage level or tier can be tracked by a set of local state indications and a set of essence state indications. The essence state indication can be tracked 'externally' from a storage layer or tier directory (e.g., in a directory of another cache level, in a hub between cache levels, etc.). One storage level can control operations based upon the local state indications and another storage level can control operations based in least in part upon an essence state indication.

Information coherency maintenance systems and methods

Various embodiments of microprocessors and methods of operating a microprocessor during runahead operation are disclosed herein. One example method of operating a microprocessor includes identifying a runahead-triggering event associated with a runahead-triggering instruction and, responsive to identification of the runahead-triggering event, entering runahead operation and inserting the runahead-triggering instruction along with one or more additional instructions in a queue. The example method also includes resuming non-runahead operation of the microprocessor in response to resolution of the runahead-triggering event and re-dispatching the runahead-triggering instruction along with the one or more additional instructions from the queue to the execution logic.

Queued instruction re-dispatch after runahead

The description covers a system and method for operating a micro-processing system having a runahead mode of operation. In one implementation, the method includes providing, for a first portion of code, a runahead correlate. When the first portion of code is encountered by the micro-processing system, a determination is made as to whether the system is operating in the runahead mode. If so, the system branches to the runahead correlate, which is specifically configured to identify and resolve latency events likely to occur when the first portion of code is encountered outside of runahead. Branching out of the first portion of code may also be performed based on a determination that a register is poisoned.

Branching to alternate code based on runahead determination

Embodiments related to managing potentially invalid results generated/obtained by a microprocessor during runahead are provided. In one example, a method for operating a microprocessor includes causing the microprocessor to enter runahead upon detection of a runahead event. The example method also includes, during runahead, determining that an operation associated with an instruction referencing a storage location would produce a potentially invalid result based on a value of an architectural poison bit associated with the storage location and performing a different operation in response.

Managing potentially invalid results during runahead

Growing community of inventors

Los Gatos, CA, United States of America

Guillermo Juan Rozas