Synopsys, Inc.

Guillaume Plassan

Mohammad Homayoun Movahed-Ezazi

Mohamed Shaker Sarwary

Fahim Rahim

Barsneya Chakrabarti

Lisa R McIlwain

Dipti Ranjan Senapati

Hans-Joerg Peter

Some aspects of this disclosure are directed to implementing formal gated clock conversion for field programmable gate array (FPGA) synthesis. For example, some aspects of this disclosure relate to a method, including receiving network representation of a circuit design, determining a gated clock function corresponding to a target component of the network representation, and constructing an edge function based at least in part on the gated clock function. The method further includes performing a minimization of the edge function, and in response to a determination that the minimization of the edge function comprises a first term and a second term, providing a clock enable signal to the target component based on the first term, and providing a clock signal to the target component based on the second term.

Formal gated clock conversion for field programmable gate array (FPGA) synthesis

Formal verification techniques are used to extract valid clock modes from a hardware description of the clock network. In one aspect, the clock network includes primary clocks and configuration signals as inputs, and also includes derived clocks within the clock network. The derived clocks are configurable for different clock modes according to the values of the configuration signals. A parametric liveness property checking is applied to the derived clocks, where the configuration signals are parameters for the parametric liveness property checking. The parametric liveness property checking infers which values of the configuration signals result in valid clock modes for the derived clocks.

Formal clock network analysis, visualization, verification and generation

Growing community of inventors

Mérignac, France

Guillaume Plassan