Nxp USA, Inc.

Guillaume Mouret

Yann Cargouet

Alexis Nathanael Huot-Marchand

Thierry Michel Alain Sicard

Tristan Bosvieux

John M Pigott

Thierry Sicard

Laurent Bordes

Guerric Panis

Pascal Sandrez

Matthew Bacchi

Soufiane Serser

Alexis Nathanaël Huot-Marchand

Nicolas Astruc

Fabien Viemon

Thierry M Alain Sicard

The disclosure relates to a transceiver physical layer interface. Example embodiments include a transmission line transceiver () comprising: first and second terminals (); a control module (); an amplifier module () connected between the control module () and the first and second terminals (); a switchable termination resistance circuit () connected between the first and second terminals (), the switchable termination resistance circuit () comprising a termination resistance () connected in series with a switch () controllable by the control module (); a pair of series connected resistors () connected between the first and second terminals (); a capacitor () connected between a node () connecting the pair of series connected resistors () and a common node (), wherein the control module () is configured to open the switch () to disconnect the termination resistance () during transmission of a signal via a transmission line () capacitively connected to the first and second terminals ().

Transceiver physical layer interface

A calibration apparatus for a communication system. The calibration apparatus is configured to: a) set a variable termination-resistance at a receiver to a predetermined value; b) cause a transmitter to send a calibration pattern to the receiver by: setting the differential voltage on the line to a non-zero value during a non-zero-phase; and setting the differential voltage on the line to zero during a subsequent zero-phase; c) compare the differential voltage on the line during the zero-phase with a reduced-bit-value-threshold, wherein the reduced-bit-value-threshold is less than a bit-value-threshold that is used during active communication. If the differential voltage on the line during the zero-phase exceeds the reduced-bit-value-threshold, then the calibration apparatus adjusts the value of the variable termination-resistance and returns to step b). If the differential voltage on the line during the zero-phase does not exceed the reduced-bit-value-threshold, then the calibration apparatus stores the current value of the variable termination-resistance for subsequent use during active communication.

Calibration apparatus for a communication system

A bandgap reference circuit includes a first current generator having first and second bipolar transistors for generating a first current that varies proportionally as a function of temperature. A second current generator includes a field effect transistor for generating a second current that varies inversely as a function of temperature. A trimming circuit includes a third bipolar transistor sized to match the first bipolar transistor, a third current generator having a second field effect transistor coupled to a collector and base of the third bipolar transistor to generate a third current based on a base current of the third bipolar transistor, and a trim control circuit configured to modify the second current by adding the third current to or subtracting the third current from the second current based on a trim control signal. A bandgap reference current is generated by summing the first current and the modified second current.

Bandgap reference circuit with trimming circuit

A switchable termination resistance circuit for a transceiver physical layer interface. Example embodiments include a switchable termination resistance circuit for a transmission line transceiver, the switchable termination resistance circuit comprising: first and second terminals for connection to a transmission line; first and second NMOS termination resistance switches having source connections connected together at a midpoint node and gate connections connected to an input node; a first resistor connected between the first terminal and a drain connection of the first NMOS termination resistance switch; a second resistor connected between the second terminal and a drain connection of the second NMOS termination resistance switch; a Zener diode having a cathode side connected to the input node and an anode side connected to the midpoint node; and a branch comprising a second Zener diode, a branch diode, a branch NMOS switch and a branch PMOS switch in a series connected arrangement between the midpoint node and a ground line.

Switchable termination resistance circuit

The present disclosure relates to a transceiver () comprising a first and second terminal, a signal generation unit a signal generation unit () for generating a differential output voltage (Vout) between the terminals, a sensor unit () configured to measure an electric current (Iout) when flowing through one of the terminals, and a control unit () for controlling the signal generation unit, wherein the control unit is configured to control the signal generation unit during a calibration phase to generate a predetermined differential output voltage reference pattern (), wherein the sensor unit is configured to measure a calibration current unit during the calibration phase, and wherein the control unit is configured to calibrate the signal generation unit depending on the calibration current. The present disclosure also relates to a method for the transceiver.

Transceiver for transmitting and receiving signals and method for the transceiver

A low voltage bandgap reference circuit () is provided which includes a first current generator () having first and second circuit branches which include, respectively, first and second bipolar transistors having different sizing reference values for generating a first current at a first resistor that varies proportionally as a function of temperature; a second current generator () having a third circuit branch which includes one or more field effect transistors and no bipolar transistors for generating a second current that varies inversely as a function of temperature; and a third circuit () connected to generate a bandgap reference current in response to the first current and the second current.

Bandgap current architecture optimized for size and accuracy

The present application relates to a sub-bandgap reference source circuit, which comprises a current mirror source, a first branch comprising a first BJT and a second branch comprising a second BJT, the first BJT having an emitter current density lower than an emitter current density of the second BJT, the first branch and the second branch being connected at a first node coupled to ground; a first voltage divider comprising first and second resistances coupled in series, the first resistance being coupled between a base terminal of the first BJT and a second node, the second resistor being coupled to ground; a second voltage divider comprising first and second resistances coupled in series, the first resistance being coupled between the second node and a base terminal of the second BJT, the second resistance being coupled to the first node; and an output terminal coupled to the second node.

Sub-bandgap reference voltage source

A detector () detects an unwanted oscillation generated by a closed-loop system () due to disconnection, improper usage, or absence of a stability-controlling element () necessary for the closed-loop system to function properly. An integrated circuit () includes the closed-loop system, the detector, and a supervisory system () that disables the closed-loop system upon disconnection of the stability-controlling element from the closed-loop system.

Growing community of inventors

Toulouse, France

Guillaume Mouret