Koninklijke Philips Corporation N.V.

Guillaume E A Lousberg

Franciscus G M De Jong

Mathias N M Muris

Robertus M W Raaijmakers

Erik Jan Marinissen

Paul Wielage

An electronic circuit comprises a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects. A main unit implements a normal mode function of the electronic circuit. A test unit tests the interconnects. The electronic circuit has a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit. In the test mode the test unit is operable as a low complexity memory via the I/O nodes.

Circuit with interconnect test unit

A memory array, and in particular, an embedded memory array is tested by interfacing to a stimulus generator and a response evaluator pair. In a non-test condition the pair is steered in a transparent mode, and in a test condition in a stimulus generating mode and a response evaluating mode respectively. In a subsequent array repair condition row and/or column-based repair intervention are allowed. In particular, the evaluator will evaluate correspondence between successive fault patterns, and further in a fault response signalizing mode to external circuitry on the basis of a predetermined correspondence between an earlier fault pattern and a later fault pattern signalize one of the two compared patterns only in the form of a lossless compressed response pattern.

Method and apparatus for testing a memory array using compressed responses

Circuit with interconnect test unit and a method of testing interconnects between a first and a second electronic circuit

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Eindhoven, Netherlands

Guillaume E A Lousberg