Koninklijke Philips Corporation N.v.

Nxp B.v.

Dsp Group Switzerland Ag

Dxp B.v.

Guillaume De Cremoux

Insun Van Loo

Jan Dikken

Ferry Nieuwhoff

Yovgos Christoforou

Aykut Kenc

Wilhelmus Johannes Remigius Willemsen

An improved capacitive feedback circuit () comprises a feedback capacitor () having its output terminal connected to a high-impedance node (N). More particularly, the improved capacitive feedback circuit comprises a first branch () having a bias current source (), an amplifying element (), and a current sensor () connected in series, the amplifying element having a high-impedance control terminal (). The feedback capacitor () has its output terminal connected to said control terminal (). A current-to-voltage converting feedback loop () has a high-impedance output terminal () connected to said feedback capacitor output terminal.

Capacitive feedback circuit

A three state class D amplifier () comprising a first signal path () and a second signal path (') substantially identical with the first signal path (). Each of the signal paths (&#x2032;) comprises respective first and second low-pass filter means (&#x2032;) coupled to respective input signals (Vn, Vp) provided by input means (Inp, In, Ip), first and second ends (A, B) of a load () and to an pulse generator () providing a signal having a frequency substantially higher than a frequency of the input signals (Vn, Vp) for generating respective first and second low-pass filtered signals (SUP, SDW). The low-pass filtered signals (SUP, SDW) are inputted to respective comparing means (&#x2032;). The comparing means (&#x2032;) are coupled to a threshold generator () coupled to the input means (Inp, In, Ip) and to first and second reference signals (Vmax, Vmin) representing an estimation of a maximum and a minimum signal value through the load () and generating an alternating threshold signal (THRES) that is inverse proportional to a difference between the first and second input signals (Vn, Vp) for maintaining a relative high gain of the amplifier in an idle state.

Three state class D amplifier

A semiconductor switch comprises two NMOS transistors coupled in an anti-series arrangement, and a gate control circuit coupled to both gates of the NMOS transistors. Both drains of the NMOS transistors are interconnected, and the gate control circuit is coupled to the drains interconnection. The required chip area is halved compared to prior art switches. Pumping the gates to higher voltages may cause a further reduction of the sizes of the NMOS transistors. In addition, advantageously, a large range of input and output voltages can be allowed between the sources of the NMOS transistors, whereby the sources act as input and output respectively of the switch, thus allowing application of the switch in a broad technical field.

Bi-directional double NMOS switch

A voltage comparator with comparing means that are energized upon the occurrence of a clock-edge and that are de-energized when the comparison operation is completed. The comparing means are preceded by a voltage divider (D) for dividing the voltage to be compared and a switch (S) in series with the voltage divider for preventing current flow through the voltage divider when the comparing means are de-energized.

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Nijmegen, Netherlands

Guillaume De Cremoux