Stmicroelectronics S.a.

Maxim Integrated Products, Inc.

Commissariat a L'energie Atomique

Intel Corporation

Triquint Semiconductor Corporation

Other

Stmicroelectronics (crolles 2) Sas

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Guillaume Bouche

Pascal Ancey

Ralph N Wall

Sudarsan Uppili

Sean T Ma

Andy Chih-Hung Wei

Fabrice Casset

Grégory Caruyer

Fanling Hsu Yang

Haim Ben Hamou

Thomas Skotnicki

Stéphane Monfray

Olivier Menut

Bernard Andre

David Snyder

Nicolas Abelé

Carlton Stuebing

Nicolas Sillon

Alexandre Talbot

Christopher S Blair

Karim Segueni

David E Hart

Ed Godshalk

Albert M Bergemont

Philippe Robert

Bernard Viala

Maurice Rivoire

Guy Parat

Edward Martin Godshalk

Herve Jaouen

Daniel Gloria

Jean-Christophe Giraudin

Daniel Saias

Eric Sabouret

Herv&eacute; Jaouen

Timothy K McGuire

Garth G Sundberg

Rick D Lutz

David Harper

Sébastien Montusclat

Rivoire Maurice

Nick Smears

Roberto Gonella

Michel Varrot

Fabrice Cassett

Sandrine Couderc

David McDonald

Disclosed herein are isolation regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC component may include: a first region including silicon; a second region including alternating layers of a second material and a third material, wherein the second material includes silicon and germanium, the third material includes silicon, and individual ones of the layers in the second region has a thickness that is less than 3 nanometers; and a third region including alternating layers of the second material and the third material, wherein individual ones of the layers in the third region has a thickness that is greater than 3 nanometers, and the second region is between the first region and the third region.

Isolation regions in integrated circuit structures

Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first dielectric material continuously around the first gate metal; and a second dielectric material continuously around the second gate metal, wherein the first dielectric material and the second dielectric material are present between the first gate metal and the second gate metal.

Gate spacing in integrated circuit structures

Disclosed herein are source/drain regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: an array of channel regions, including a first channel region and an adjacent second channel region; a first source/drain region proximate to the first channel region; a second source/drain region proximate to the second channel region; and an insulating material region at least partially between the first source/drain region and the second source/drain region.

Source/drain regions in integrated circuit structures

Discussed herein is device contact sizing in integrated circuit (IC) structures. In some embodiments, an IC structure may include: a first source/drain (S/D) contact in contact with a first S/D region, and a second S/D contact in contact with a second S/D region, wherein the first S/D region and the second S/D region have a same length, and the first S/D contact and the second S/D contact have different lengths.

Device contact sizing in integrated circuit structures

A semiconductor device including a VDMOS device formed therein includes a terminal, or contact, to the drain region of the VDMOS device from the frontside of the device. In one or more implementations, a semiconductor device includes a semiconductor substrate having a first surface and a second surface and a vertical diffused metal-oxide-semiconductor device formed within the semiconductor substrate. The vertical diffused metal-oxide-semiconductor device includes at least one source region formed proximate to the first surface and at least one drain region formed proximate to the second surface. A through-substrate via is formed within the semiconductor substrate, and the through-substrate via electrically connected to the drain region. The through-substrate via provides an electrical interconnection to the drain region from the first surface.

Vertical semiconductor device having frontside interconnections

Semiconductor devices, such as laterally diffused metal oxide semiconductor (LDMOS) devices, are described that have a field plate connected to a gate of the device. In one or more implementations, the semiconductor devices include a substrate having a source region of a first conductivity type and a drain region of the first conductivity type. A gate is positioned over the surface and between the source region and the drain region. The gate is configured to receive a voltage so that a conduction region may be formed at least partially below the gate to allow majority carriers to travel between the source region and the drain region. The device also includes a field plate at least partially positioned over and connected to the gate. The field plate is configured to shape an electrical field generated between the source region and the drain region when a voltage is applied to the gate.

LDMOS with field plate connected to gate

A semiconductor device is described that includes a first electrical circuit and a second electrical circuit formed on a semiconductor on insulator wafer. The semiconductor on insulator wafer has a layer of semiconducting material formed over a buried layer of insulating material formed over a supporting layer of material. A wide deep trench is formed in the semiconductor on insulator wafer to galvanically isolate the first electrical circuit from the second electrical circuit. The first electrical circuit and the second electrical circuit are coupled together for exchanging energy between the galvanically isolated electrical circuits.

Integrated monolithic galvanic isolator

Semiconductor devices, such as LDMOS devices, are described that include an interlayer-dielectric layer (ILD) region having a thickness of at least two and one half (2.5) microns to increase the maximum breakdown voltage. In one or more implementations, the semiconductor devices include a substrate having a source region and a drain region formed proximate to a surface of the substrate. A gate is positioned over the surface and between the source region and the drain region. An ILD region having a thickness of at least two and one half (2.5) microns is formed over the surface and the gate of the device. The device also includes one or more field plates configured to shape an electrical field generated between the source region and the drain region when a voltage is applied to the gate.

LDMOS with thick interlayer-dielectric layer

A pump having: a cavity formed inside an insulating substrate, the upper part of the substrate being situated near the cavity having an edge; a conductive layer covering the inside of the cavity up to the edge and optionally covering the edge itself; a flexible membrane made of a conductive material placed above the cavity and resting against the edge; a dielectric layer covering the conductive layer or the membrane whereby insulating the portions of the conductive layer and of the membrane that are near one another; at least one aeration line formed in the insulating substrate that opens into the cavity via an opening in the conductive layer, and; terminals for applying a voltage between the conductive layer and the membrane.

Method of forming a cooling device for an integrated circuit

Embodiments of the present invention provide systems, devices and methods for improving both the bandwidth of a BAW resonator bandpass filter and the suppression of out-of-band frequencies above the passband. In various embodiments of the invention, blocker inductors are located in series between the filter input and the filter output to realize both bandwidth enhancement and improved out-of-band frequency rejection. For example, a first blocker inductor may be located at the input and a second blocker inductor may be located at the output of a BAW resonator bandpass filter.

BAW resonator filter bandwidth and out-of-band frequency rejection

A method of fabricating a piezoelectric resonator includes providing a bottom electrode and a piezoelectric layer coupled to the bottom electrode. A bottom metal layer of a top electrode is deposited on the piezoelectric layer. A top metal layer of the top electrode is deposited on the bottom metal layer. A photoresist layer is deposited on the top metal layer. The photoresist layer is patterned and etched. The top metal layer is patterned and etched while the etched photoresist layer remains. The bottom metal layer is patterned and etched such that an entire perimeter side surface of the top metal layer is recessed relative to a perimeter edge of the bottom metal layer. The etched photoresist layer is removed. A passivation layer is deposited on the top and bottom metal layers such that the top and bottom metal layers are isolated from a subsequent metal etch step.

Method to control BAW resonator top electrode edge during patterning

A piezoelectric layer is coupled to a bottom electrode in a method of fabricating a piezoelectric resonator. A bottom metal layer of a top electrode is deposited on the piezoelectric layer. The bottom metal layer is patterned and etched. A top metal layer of the top electrode is deposited on the etched bottom metal layer. The top metal layer is patterned and etched. An interconnect metal layer is deposited on the etched top metal layer and the piezoelectric layer such that the interconnect metal layer isolates the bottom metal layer from subsequent etch steps.

Process of making a BAW resonator bi-layer top electrode

Integrated circuit cooling device

A microresonator comprising a single-crystal silicon resonant element and at least one activation electrode placed close to the resonant element, in which the resonant element is placed in an opening of a semiconductor layer covering a substrate, the activation electrode being formed in the semiconductor layer and being level at the opening.

Microresonator

Growing community of inventors

Grenoble, France

Guillaume Bouche