Globalfoundries Inc.

Imec Vzw

Globalfoundries U.S. Inc.

International Business Machines Corporation

Globalfoundaries Inc.

Guillaume Bouche

Jason Eugene Stephens

Andy C Wei

Andy Chih-Hung Wei

Tuhin Guha Neogi

Mark Alexander Zaleski

Ruilong Xie

Lars W Liebmann

Nicholas V Licausi

Jia Zeng

Jing Wan

Jongwook Kye

Andre P Labonte

Sudharshanan Raghunathan

Xiang Hu

Huy Cao

Gabriel Padron Wells

Shao Ming Koh

Chanro Park

Daniel Chanemougame

Jeremy Austin Wahl

Nigel Graeme Cave

Deniz Elizabeth Civay

Craig Child

Veeraraghavan S Basker

Hui Zang

Shreesh Narasimha

Huang Liu

Lei Yuan

Lei Sun

Michael Vincent Aquilino

Byoung Youp Kim

David Michael Permana

Kangguo Cheng

Jinping Liu

Vimal Kumar Kamineni

Jin Ping Liu

Keith Howard Tabakman

Julien Ryckaert

David C Pritchard

Juergen Boemmels

Richard Farrell

Mahender Kumar

Youngtag Woo

Xintuo Dai

Vikrant Kumar Chauhan

Sandeep Gaan

Patrick D Carpenter

Shyam Pal

Ajey Poovannummoottil Jacob

Julien Frougier

Fee Li Lie

Xiuyu Cai

Min Gyu Sung

Hoon Sik Kim

Hiroaki Niimi

Haiting Wang

Xunyuan Zhang

Laertis Economikos

Kisik Choi

Steven J Bentley

Yan E Wang

Scott D Luning

Gerard M Schmid

Stuart A Sieg

Haigou Huang

Bartlomiej Jan Pawlak

Guoxiang Ning

Roderick Alan Augur

Daniel J Jaeger

Scott Beasor

Wenhui Wang

Mark V Raymond

Geng Han

David E Brown

Bharat V Krishnan

Linus Jang

Akshey Sehgal

Frederic Lazzarino

Lei L Zhuang

Dae Geun Yang

Ji Xu

David Doman

Songkram Srivathanakul

Haifeng Sheng

Lun Zhao

Chang Ho Maeng

Kai Sun

Nicholas LiCausi

Ahmed Hassan

Rama Kambhampati

Mariappan Hariharaputhiran

Tien-Ying Luo

Erik Geiss

Cuiqin Xu

Jiong Li

Patrick Ryan Justison

Eric S Kozarsky

Kenneth Andrew Bates

The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.

Self aligned buried power rail

Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.

Multiple fin finFET with low-resistance gate structure

A method for forming an interconnection structure for a semiconductor device is provided. The method includes: (i) forming a conductive layer on an insulating layer; (ii) forming above the conductive layer a first set of mandrel lines of a first material; (iii) forming a set of spacer lines of a second material different from the first material, wherein the spacer lines of the second material are formed on sidewalls of the first set of mandrel lines; (iv) forming a second set of mandrel lines of a third material different from the first and second materials, wherein the second set of mandrel lines fill gaps between spacer lines of the set of spacer lines; (v) cutting at least a first mandrel line of the second set of mandrel lines into two line segments separated by a gap by etching said first mandrel line of the second set of mandrel lines selectively to the set of spacer lines and the first set of mandrel lines, cutting at least a first mandrel line of the first set of mandrel lines into two line segments separated by a gap by etching said first mandrel line of the first set of mandrel lines selectively to the set of spacer lines and the second set of mandrel lines; (vi) removing the set of spacer lines, selectively to the first and second sets of mandrel lines, thereby forming an alternating pattern of mandrel lines of the first set of mandrel lines and mandrel lines of the second set of mandrel lines; and (vii) patterning the conductive layer to form a set of conductive lines, wherein the patterning comprises etching while using the alternating pattern of mandrel lines of the first and second sets of mandrel lines as an etch mask.

Method for forming an interconnection structure

Methods pattern a sacrificial material on an etch mask into mandrels using optical mask lithography, form a conformal material and a fill material on the mandrels, and planarize the fill material to the level of the conformal material. Such methods pattern the fill material into first mask features using extreme ultraviolet (EUV) lithography. These methods partially remove the conformal material to leave the conformal material on the sidewalls of the mandrels as second mask features. Spaces between the first mask features and the second mask features define an etching pattern. The spacing distance of the mandrels is larger than the spacing distance of the second mask features. Such methods transfer the etching pattern into the etch mask material, and subsequently transfer the etching pattern into an underlying layer. Openings in the underlying layer are filled with a conductor to form wiring in the etching pattern.

Hybrid optical and EUV lithography

A semiconductor device includes: (i) a substrate; (ii) a first elongated semiconductor structure extending in a first horizontal direction along the substrate and protruding vertically above the substrate, wherein a first set of source/drain regions are formed on the first semiconductor structure; (iii) a second elongated semiconductor structure extending along the substrate in parallel to the first semiconductor structure and protruding vertically above the substrate, wherein a second set of source/drain regions are formed on the second semiconductor structure; and (iv) a first set of source/drain contacts formed on the first set of source/drain regions, wherein a first source/drain contact of the first set of source/drain contacts includes: (a) a vertically extending contact portion formed directly above a first source/drain region of the first set of source/drain regions, and (b) a via landing portion protruding horizontally from the vertically extending contact portion in a direction towards the second semiconductor structure.

Semiconductor device and method

A semiconductor structure includes a substrate having a first region and a second region, a first source/drain disposed on the substrate in the first region, an interlevel dielectric (ILD) disposed on the source/drain, and a first gate disposed on the substrate. The semiconductor structure further includes a first contact trench within the ILD extending to the first source/drain, a first trench contact within the first contact trench, and a first source/drain contact trench extending to the first trench contact. The semiconductor structure further includes a cross couple contact trench within the ILD, and a cross couple contact disposed in the cross couple contact trench in contact with the first gate and the first trench contact. The cross couple contact couples the first source/drain and the first gate.

Transistor with recessed cross couple for gate contact over active region integration

Methods for forming a cut between interconnects and structures with cuts between interconnects. A layer is patterned to form first, second, and third features having a substantially parallel alignment with the second feature between the first feature and the third feature. A sacrificial layer is formed that is arranged between the first and second features and between the second and third features. The sacrificial layer is patterned to form a cut between the first and second features from which a portion of the sacrificial layer is fully removed and to form a cavity in a portion of the sacrificial layer between the second and third features. A dielectric layer is formed inside the cut between the first and second features. After depositing the section of the dielectric material and forming the dielectric layer, the sacrificial layer is removed.

Self-aligned cuts in an interconnect structure

Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged.

Merged gate and source/drain contacts in a semiconductor device

The present disclosure relates to semiconductor structures and, more particularly, to interrupted small block shape structures (e.g., cut metal lines forming cell boundaries) and methods of manufacture. The structure includes: a plurality of wiring lines with cuts that form a cell boundary; and at least one wiring line extending beyond the cell boundary and which is continuous from cell to cell.

Interrupted small block shape

A method includes forming an isolation pillar between first and second active nanostructures for adjacent FETs. When a first WFM surrounding the second active nanostructure is removed as part of a WFM patterning process, creating a discontinuity in the first metal. The pillar or the discontinuity in the first metal on the part of the pillar prevent the etching from reaching and removing the first WFM on the first active nanostructure. The isolation pillar creates a gate cut isolation in a selected gate region, and can be shortened in another gate region to allow for gate sharing between adjacent FETs.

Work function metal patterning for N-P spaces between active nanostructures using unitary isolation pillar

At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

Methods, apparatus and system for a passthrough-based architecture

The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of defining routing tracks for a standard cell semiconductor device, and to the standard cell semiconductor device fabricated using the method. In one aspect, a method of defining routing tracks in a target layer over a standard cell semiconductor device includes forming mandrels and forming a first set and a second set of spacers for defining the routing tracks. The standard cell semiconductor device includes a device layer and the routing tracks for contacting a device layer. The routing tracks include at least two pairs of off-center routing tracks, a central routing track arranged between the pairs of off-center routing tracks, and at least two edge tracks arranged on opposing sides of the at least two pairs of off-center routing tracks. A minimum distance between an off-center routing track and the central routing track next to the off-center routing track is smaller than a minimum distance between adjacent off-center routing tracks.

Method of patterning target layer

Disclosed herein are a method of forming stacked elongated nanoshapes (NSs) (e.g., stacked nanowires (NWs)) of different semiconductor materials above a substrate, a method of forming different devices (e.g., stacked field effect transistors (FETs) having different type conductivities) using the stacked NSs and the resulting structures. In the methods, stacked elongated NSs made of the same first semiconductor material can be formed above a substrate. The stacked elongated NSs can include at least a first NS and a second NS above the first NS. The second NS can then be selectively processed in order to convert the second NS from the first semiconductor material to a second semiconductor material. The first and second NSs can subsequently be used to form first and second devices, respectively, wherein the second device is stacked above the first device. The first and second device can be, for example, first and second FETs, respectively.

Stacked elongated nanoshapes of different semiconductor materials and structures that incorporate the nanoshapes

Growing community of inventors

Albany, NY, United States of America

Guillaume Bouche