Cadence Design Systems, Inc.

Guilherme Henrique De Sousa Santos

Chung-Wah Norris Ip

Georgia Penido Safe

Victor Markus Purri

Adriana Cassia Rossi De Almeida Braz

Mirlaine Aparecida Crepalde

Ronalu Augusta Nunes Barcelos

Regina Mara Amaral Fonseca

Lucas Luz Reckziegel

Glauber Tadeu De Sousa Carmo

Augusto Amaral Mafra

Valdir Antoniazzi Júnior

Marcus Vincius Da Mata Gomes

Hudson Dyele Pinheiro De Oliveira

Disclosed are techniques for verifying connectivity of an electronic design. These techniques Identify connectivity information for a design description of an electronic design, generate a partition of a plurality of partitions for the connectivity information by partitioning the connectivity into the plurality of partitions based in part or in whole upon one or more factors, and performing a pre-proof verification flow on the partition by proving or disproving at least one connection candidate of a plurality of connection candidates for the partition to generate proof results for the partition. These techniques may further additionally generate a property for a connection candidate that fails to result in definitive proof results and prove or disprove the property with formal methods or techniques.

Methods, systems, and computer program product for connectivity verification of electronic designs

The present disclosure relates to a method for debugging associated with formal verification of an electronic design. Embodiments may include performing, using a processor, an initial formal verification of an electronic design. Embodiments may further include identifying one or more counter-examples associated with one or more assertion properties of the electronic design or identifying one or more cover-traces associated with one or more cover properties of the electronic design. Embodiments may further include generating a trace core for each of the one or more counter-examples or cover-traces, wherein each trace core includes a minimal representation of the counter-example or cover-trace. Embodiments may further include identifying a similarity between a plurality of the trace cores and clustering the plurality of trace cores having the similarity.

System, method, and computer program product for property clustering associated with formal verification of an electronic circuit design

Disclosed are techniques for implementing electronic designs with automatic connectivity information extraction. These techniques traverse at least a portion of an electronic design, classify or categorize circuit component designs encountered during traversal into multiple categories, extract connectivity information for the at least the portion of the electronic design based in part or in whole upon one or more criteria, and devising the at least the portion of the electronic design with at least the connectivity information. A connectivity data structure may be constructed with the extracted connectivity information. A plurality of circuit component designs categorized into the same category may be grouped into a single element in the connectivity data structure.

Methods, systems, and articles of manufacture for automatic extraction of connectivity information for implementation of electronic designs

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Belo Horizonte, Brazil

Guilherme Henrique De Sousa Santos