Centre National De La Recherche Scientifique

Guilhem Larrieu

Emmanuel Dubois

Adrien Casanova

A platform for cellular interfacing including at least one nano-probe based on nano-wires each having a conductive extremity intended to be in contact with a cell. The platform has at least one field-effect transistor called a nano-FET positioned at a predetermined distance from the nano-probe.

Nanostructure platform for cellular interfacing and corresponding fabrication method

A process for fabricating a field-effect transistor device () implemented on a network of vertical nanowires (), includes: producing a source electrode () and a drain electrode () at each end of each nanowire () symmetrically relative to the gate electrode of each elementary transistor implemented on a nanowire; creating a gate electrode by depositing a layer () of conductive material around a layer () of dielectric material that surrounds a portion of each nanowire (), a single conductive layer () being used for all of the nanowires and the thickness of the conductive layer corresponding to the gate length of the transistor device; and insulating each electrode with a planar layer () of a dielectric material in order to form a nanoscale gate and in order to insulate the contacts of each elementary transistor between the gate and the source and the gate and the drain.

Process for fabricating a field-effect transistor device implemented on a network of vertical nanowires, the resulting transistor device, an electronic device comprising such transistor devices and a processor comprising at least one such device

This method for making complementary p and n MOSFET transistors with Schottky source and drain electrodes controlled by a gate electrode, comprising: making source and drain electrodes from a single silicide for both p and n transistors; segregating first impurities from groups II and III of the periodic table at the interface between the silicide and the channel of the p transistor, the complementary n transistor being masked; and segregating second impurities from groups V and VI of the periodic table, at the interface between the silicide and the channel of the n transistor, and the complementary p transistor being masked.

Method for making complementary P and N MOSFET transistors, electronic device including such transistors, and processor including at least one such device

Growing community of inventors

Baziege, France

Guilhem Larrieu