Chinese Academy of Sciences

Beijing Superstring Academy of Memory Technology

Other

Guilei Wang

Junfeng Li

Chao Zhao

Jinbiao Liu

Huilong Zhu

Huaxiang Yin

Chunlong Li

Zhengyong Zhu

Tao Yang

Jun Luo

Xiaolong Ma

Changliang Qin

Xiangsheng Wang

Henry H Radamson

Bokmoon Kang

Xuezheng Ai

Wenhua Gui

Jianfeng Gao

Hui Li

Junjie Li

Yao M Wang

Miao Xu

Yanbo Zhang

Qiang Xu

Jin Dai

Zhenzhen Kong

A semiconductor device, manufacturing method therefor, and electronic equipment are provided. The manufacturing method includes: alternately depositing sacrificial layers and insulation layers to obtain a stacked structure; forming in the stacked structure a plurality of via holes distributed at intervals, and forming dummy word lines in the via holes; forming a first trench penetrating through the stacked structure every two via holes apart; forming a plurality of grooves by re-etching the plurality of insulation layers within the first trench, wherein two grooves of each insulation layer in two first trenches respectively expose partial side walls of a dummy word line; forming conductive layers within the two grooves corresponding to each insulation layer, wherein a conductive layer within each groove surrounds two exposed dummy word lines; and disconnecting a conductive layer surrounding a dummy word line to form a first electrode and a second electrode of a transistor.

Semiconductor device, manufacturing method therefor, and electronic equipment

A semiconductor device including a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a semiconductor material causing an increased ON current and/or a reduced OFF current as compared to Si.

Semiconductor device, method of manufacturing the same and electronic device including the same

Provided are a semiconductor device and manufacturing method thereof, and an electronic device. The semiconductor device includes multiple storage cells distributed in a direction perpendicular to a base substrate, the multiple storage cells include multiple transistors and capacitors distributed in different layers and stacked in the direction perpendicular to the base substrate; a word line penetrating different layers and extending in the direction perpendicular to the base substrate; a transistor includes a first source/drain electrode, a second source/drain electrode and a semiconductor layer surrounding a sidewall of the word line; first insulating layers and conductive layers alternately distributed in the direction perpendicular to the base substrate, at least one first hole penetrating the different layers; and the second electrode of the capacitor includes an inner electrode disposed in the first hole on the first electrode.

Semiconductor device, manufacturing method therefor, and electronic device

A semiconductor memory device and a manufacturing method thereof, a reading/writing method, an electronic device and a memory circuit are provided. A transistor is provided in each memory cell in the semiconductor memory device. A gate electrode and an auxiliary electrode are provided in the transistor, and the auxiliary electrode is electrically connected to a drain electrode. During a writing operation, a first voltage is applied to the gate electrode through a word line, and an electrical signal is applied to a source electrode through a bit line according to the external input data. During a reading operation, a second voltage is applied to the auxiliary electrode through the word line by using the influence of the voltage on the auxiliary electrode on the threshold voltage of the transistor (the size of the second voltage is between the threshold voltage of the transistor when storing '1' and the threshold voltage of the transistor when storing “0”), and then the data is read by detecting the size of the output current of the field effect transistor.

Semiconductor memory device, manufacturing method thereof and electronic device

A memory comprises a substrate, and word lines, bit lines and memory cells located on one side of the substrate. Each of the memory cells comprises a transistor comprising: a semiconductor layer comprising a source contact region, a channel region and a drain contact region connected sequentially; a primary gate electrically connected to one of the word lines; a source electrically connected to one of the bit lines and the source contact region of the semiconductor layer, respectively; a drain electrically connected to the drain contact region of the semiconductor layer; and a secondary gate electrically connected to the drain, wherein an orthographic projection of the primary gate on the substrate and an orthographic projection of the secondary gate on the substrate are at least partially overlapped with an orthographic projection of the channel region of the semiconductor layer on the substrate, respectively.

Memory and manufacturing method thereof, and electronic device

A semiconductor device and a method for manufacturing the semiconductor device. Multiple stacks and an isolation structure among the multiple stacks are formed on a substrate. Each stack includes a first doping layer, a channel layer and a second doping layer. For each stack, the channel layer is laterally etched from at least one sidewall of said stack to form a cavity located between the first doping layer and the second doping layer, and a gate dielectric layer and a gate layer are formed in the cavity. A first sidewall of each stack is contact with the isolation structure, and the at least one sidewall does not include the first side wall. Costly high-precision etching is not necessary, and therefore a device with a small size and a high performance can be achieved with a simple process and a low cost. Diversified device structures can be provided on requirement.

Semiconductor device and method for manufacturing the same

A method for manufacturing a semiconductor device, comprising: forming a gate trench on a substrate; forming a gate dielectric layer and a metal gate layer thereon in the gate trench; forming a first tungsten (W) layer on a surface of the metal gate layer, and forming a tungsten nitride (WN) blocking layer by injecting nitrogen (N) ions; and filling with W through an atomic layer deposition (ALD) process. The blocking layer prevents ions in the precursors from aggregating on an interface and penetrating into the metal gate layer and the gate dielectric layer. At the same time, adhesion of W is enhanced, a process window of W during planarization is increased, reliability of the device is improved and the gate resistance is further reduced.

Method for manufacturing semiconductor device

There is provided a method for manufacturing a semiconductor device, including: providing a semiconductor substrate having a plurality of openings formed thereon by removing a sacrificial gate; filling the openings with a top metal layer having compressive stress; and performing amorphous doping with respect to the top metal layer in a PMOS device region. Thus, it is possible to effectively improve carrier mobility of an NMOS device, and also to reduce the compressive stress in the PMOS device region to ensure a desired performance of the PMOS device.

Provided is a method for manufacturing a fin structure. The method may include forming an initial fin on a substrate, forming a dielectric layer on the substrate to cover the initial fin, planarizing the dielectric layer by sputtering, and further etching the dielectric layer back to expose a portion of the initial fin, wherein the exposed portion serves as a fin.

Method for manufacturing fin structure

A method for manufacturing a FinFET device, including providing a substrate; implementing a source/drain doping on the substrate; etching the doped substrate to form a source region and a drain region; forming a fin channel between the source region and the drain region; and forming a gate on the Fin channel. The fin and the gate are formed after the source/drain doping is implemented on the substrate, so that the source/drain doping is done as a doping for a planar device, which ensures the quality of the source/drain coping and improves the property of the FinFET device.

Method for manufacturing a FinFET device

A method of depositing a tungsten (W) layer is disclosed. In one aspect, the method includes depositing a SiHbase W film on a surface of a substrate to preprocess the surface. The method includes depositing a BHbase W layer on the preprocessed surface. The SiHbase W film may be several atom layers thick. The film and base W layer may be deposited in a single ALD process, include reactive gas soak, reactive gas introduction, and main deposition operations. Forming the film may include introducing SiHgas into a reactive cavity during the gas soak operation, and introducing SiHand WFgas into the cavity during the gas introduction operation. The SiHand WFgases may be alternately introduced, for a number of cycles depending on the thickness of the tungsten layer to be deposited.

Method of depositing tungsten layer with improved adhesion and filling behavior

The present disclosure provides a method of manufacturing a semiconductor device having silicon nitride with a tensile stress, the method comprising: c1) introducing and pre-stabilizing NHgas and Ngas; c2) introducing silane; c3) igniting the gases by a radio-frequency source; c4) depositing SiN; and c5) processing the SiN by using a nitrogen ion implantation. According to the present disclosure, the nitrogen content in the SiN film can be enhanced by the nitrogen ion implantation and impinging, thereby increasing the density of the film. In this way, the acid resistance of the SiN with tensile stress is enhanced, so that the SiN with tensile stress may be integrated in a dual-strained liner of a gate-last process, so as to effectively improve the properties and reliability of the device.

Methods for manufacturing semiconductor devices

A method for manufacturing a semiconductor device is provided. The method includes forming, on a substrate, a plurality of fins extending along a first direction; forming, on the fins, a dummy gate stack extending along a second direction; forming a gate spacer on opposite sides of the dummy gate stack in the first direction; epitaxially growing raised source/drain regions on the top of the fins on opposite sides of the gate spacer in the first direction; performing lightly-doping ion implantation through the raised source/drain regions with the gate spacer as a mask, to form source/drain extension regions in the fins on opposite sides of the gate spacer in the first direction; removing the dummy gate stack to form a gate trench; and forming a gate stack in the gate trench.

A method for manufacturing a semiconductor device comprises, including forming a plurality of fins on a substrate, forming, a dummy gate stack on the fins forming a gate spacer on opposite sides of the dummy gate stack, forming source/drain trenches by etching the fins with the gate spacer and the dummy gate stack as a mask, forming source/drain extension regions on the bottom and sides of the trenches by performing lightly-doping ion implantation; and by performing epitaxial growth in and/or on the source/drain trenches, removing the dummy gate stack to form a gate trench; and forming a gate stack in the gate trench.

Method for manufacturing semiconductor device including doping epitaxial source drain extension regions

A method for eliminating contact bridge in a contact hole process is disclosed, wherein a cleaning menu comprising a multi-step adaptive protective thin film deposition process is provided, so that a stack adaptive protective thin film is formed on the sidewall of the chamber of the HDP CVD equipment. The stack adaptive protective thin film has good adhesivity, compactness and uniformity to protect the sidewall of the chamber of the HDP CVD equipment from being damaged by the plasma, and avoid the generation of defect particles, thereby improving the HDP CVD technical yield and eliminating the contact bridge phenomenon in the contact hole process.

Growing community of inventors

Beijing, China

Guilei Wang