Bull Hn Information Systems Italia S.p.a.

Honeywell Bull Italia S.p.a.

Guido Perrella

Carlo Bagnoli

Tommaso Majo

In order to arbitrate competing requests made by master elements for shared resources in a data processing system in which the masters have controlled access to the resources through a communication bus, there is provided an arbitration unit coupled to the masters and to the resources through the communication bus. There is further provided logic structure in each master for generating and sending access request signals to the arbitration unit indicating that the master needs to direct, through the communication bus, a specified resource to perform an operation, the selected resource being identified by at last one of the access request signals. The arbitration unit, upon receiving the access request signal, arbitrates among competing access request signals, which may be concurrently received from a plurality of masters, according to predetermined priority criteria. The arbitration unit includes a masking scheme responsive to at least one of the following occurrences: a) the arbitration unit having already granted access to one of the masters, through the communication bus, for directing an indicated resource to perform an operation; and b) a signal generated by at least one of the resources and received through the communication bus indicating that the resource is ready or not ready to perform an operation. The arbitration unit generates an access grant signal granting access to one master at a time based on arbitration performed among unmasked competing access request signals received through the communication bus.

Centralized arbitration system using the status of target resources to

In a data processing multiprocessor system having distributed shared resources where each system processor (7) is provided with at least a local memory (8) to which it get access through a local bus (11), and with an interface unit (10) for connection of the local bus (11) to a system bus (5) and wherein each of the system processors may have access the local memory of another processor through its own local bus, its own interface unit, the system bus and the local bus of the other processor, deadlock is prevented by providing a bypass unit (40) of the interface unit (10) for enabling access from the system bus to the local bus through the bypass unit, a block (9) connected between the local bus and the interface unit (10) for latching system bus access requests received from an agent processor on the local bus, and a block (12) for isolation of the agent processor outputs from local bus, so that each agent processor may post read/write operations in the related latching block (9) for latching bus access requests and thereafter release its own local bus without awaiting completion of the operation, whereby the local bus is available to receive access requests received from the system bus through the bypass unit (40), the operation pending in the latching block (9) being completed, if a read operation, by reconnection of the agent processor (7) and the latching block (9) to the local bus.

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Pescara, Italy

Guido Perrella