Koninklijke Philips Corporation N.v.

Nxp B.v.

Guido Jozef Maria Dormans

Robertus Dominicus Joseph Verhaar

Josephus Franciscus Antonius Maria Guelen

Antonius Maria Petrus Johannes Hendriks

Anirban Roy

Michiel Jos Van Duuren

Roy Arthur Colclaser

Donald Robert Wolters

Antonius Maria Petrus Johannes Hendricks

Joachim Christoph Hans Garbe

A temperature exposure detection system includes a plurality of nonvolatile memory cells. The memory includes memory read circuitry for reading the plurality of memory cells to determine a data retention error rate of the plurality of memory cells. The temperature exposure detection system determines a temperature exposure of the system based on the determined data retention error rate.

Temperature exposure detection based on memory cell retention error rate

A method for manufacturing on a substrate a semiconductor device with a floating-gate and a control-gate. The method includes the steps of first forming an isolation zone in the substrate, and thereafter forming the floating gate on the substrate. The method further includes extending the floating gate using spacers, and then forming the control gate over the floating gate and the spacers.

Conductive spacers extended floating gates

A method for manufacturing on a substrate a semiconductor device with improved floating-gate to control-gate coupling ratio is described. The method comprises the steps of first forming an isolation zone in the substrate, thereafter forming the floating gate on the substrate, thereafter extending the floating gate using polysilicon spacers, and thereafter forming the control gate over the floating gate and the polysilicon spacers. Such a semiconductor device may be used in flash memory cells or EEPROMs.

A method for manufacturing on a substrate () a semiconductor device with improved floating-gate to control-gate coupling ratio is described. The method comprises the steps of first forming an isolation zone () in the substrate (), thereafter forming the floating gate () on the substrate (), thereafter extending the floating gate () using polysilicon spacers (), and thereafter forming the control gate () over the floating gate () and the polysilicon spacers (). Such a semiconductor device may be used in flash memory cells or EEPROMs.

Method of manufacturing a semiconductor device, including a first baseline technology electronic circuit () and a second option technology electronic circuit () as functional parts of a system-on-chip, by:

Multilevel poly-Si tiling for semiconductor circuit manufacture

The invention relates to a semiconductor device having a byte-erasable EEPROM memory comprising a matrix of rows and columns of memory cells. In order to provide a semiconductor device having a byte-erasable EEPROM which has a reduced chip size and increased density and which is suitable for low-power applications it is proposed according to the present invention that the memory cells each comprise a selection transistor having a selection gate and, arranged in series therewith, a memory transistor having a floating gate and a control gate, the selection transistor being further connected to a source line of the byte-erasable EEPROM memory, which source line is common for a plurality of memory cells, and the memory transistor being further connected to a bit line of the byte-erasable EEPROM memory, wherein the columns of memory cells are located in separate p-type wells separated by n-type wells. Preferably, high voltage switching elements are provided for dividing global control gates into local control gates for each column of bytes.

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Nijmegen, Netherlands

Guido Jozef Maria Dormans