Itt Industries, Inc.

Guido H Nopper

Guenter Lindstedt

An MOS high-speed overflow detector for algebraic adders which add two binary numbers (a,b) in two's complement notation and contain one full adder per digit which provides a sum signal (s) and a carry signal (c) consists of a complex gate (k) made up of three two-input AND elements (u1, u2, u3). The outputs of the three AND elements are NORed. The two inputs of the first AND element (u1) are fed with the sign signal (va) of the first binary number (a) and with the inverted sign signal (vb) of the second binary number (b), respectively. The two inputs of the second AND element (U2) are fed with the sign signal (vb) of the second binary number (b) and with the sum signal (vs) of the full adder (av) of the sign digit, respectively. The two inputs of the third AND element (u3) are fed with the inverted sum signal (vs) and the inverted sign signal (va) of the first binary number (a), respectively.

Overflow detector for algebraic adders

To be able to recover from modes in which the oscillation of the voltage-controlled oscillator (V0) stops, the phase/frequency control circuit includes an RS flip-flop (RS) connected via two AND gates (U3, U3) to the two outputs (A1, A2) of the phase discriminator (P), which provide pulses for raising and lowering, respectively, the frequency of the voltage-controlled oscillator (V0). When the frequency/phase control circuit is out of lock, a pulse is generated with two monostable multivibrators (M1, M2) which passes through a signal selection circuit (S1) associated with the Q output of the RS flip-flop or through a signal selection circuit (S2) associated with the Q output of this flip-flop and controls the constant-current source (Q1) charging the smoothing device (G) or the constant-current source (Q2) discharging this device in such a way that the unwanted mode can be stopped by changing the control voltage of the oscillator (V0).

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Umkirch, Germany

Guido H Nopper