Cselt-centro Studi E Laboratori Telecomunicazioni S.p.a.

Magneti Marelli

Marelli Autronica

Guido Ghisio

Denis Bollea

Valerio Giorgetta

Daniele Marenco

Mario Fassino

Giorgio Calvi

Gianluca Monchiero

Alberto c/o Universita'di Parma Broggi

A parking-assistant system for 'multi-maneuver parking', which is designed for generating, before the parking maneuver is started, a predetermined path, via the simulation of a maneuver of exit from a parking space. The control effected by the system, during the real parking maneuver, limits itself to comparing the effective position of the vehicle with respect to the predetermined path. Said control has somewhat low computational requirements so that the system is quite reliable.

Parking-assistant system

During the piloting of the load, the current intensity and the voltage present in the load are monitored by the comparison of their values with a current threshold and with a window of permissible voltage values. When the voltage is outside the window of permissible values and/or the current falls below its threshold, a fault message is generated and the nature of the fault (open load, short circuit to earth, short circuit to the supply voltage) is also identified by the emission of a corresponding signal of a diagnostic nature. The identification of the faulty stage or stages is also provided for in the case of a circuit including several stages in parallel.

Electrical circuit, particularly an electronic power circuit for motor

The blocking circuits which, during precharge, inhibit the data passage to the AND and OR planes of a dynamic programmable logic array with NOR-NOR structure, implemented in C-MOS technology, comprise a pair of transistors with complementary channel doping, the first of which controls the signal passage to the AND or the OR plane, respectively, and the second inhibits the gates of the respective plane during precharge.

Dynamic programmable logic arrays with NOR-NOR structure implemented in

The basic element provided by the invention carries out the basic logic functions of storage and/or transfer of the data applied at the input, typical of a latch. Two ways of embodiment of the basic element having active phase at the high and low level of the clock signal are described. The basic element presents a transfer-gate transistor at the input controlled by the clock signal, followed by an inverter at whose signal leads two positive feedback networks are connected, one of which controlled by the clock signal, to stabilize the logic levels (FIG. 1).

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Turin, Italy

Guido Ghisio