Stmicroelectronics S.r.l.

St-ericsson Sa

Guido Gabriele Albasini

Enrico Temporiti Milani

Giulio Ricotti

Maurizio Zuffada

Giovanni Frattini

Giacomino Bollati

Giuseppe Cusmai

Francesco Svelto

Michele Fedeli

Matteo Repossi

Mattia Introini

A fractional-type phase-locked loop circuit is proposed for synthesizing an output signal multiplying a frequency of a reference signal by a fractional conversion factor, the circuit including means for generating a modulation value, means for generating a feedback signal dividing the frequency of the output signal by a dividing ratio, the dividing ratio being modulated according to the modulation value for providing the conversion factor on the average, means for generating a control signal indicative of a phase difference between the reference signal and the feedback signal, means for controlling the frequency of the output signal according to the control signal, and means for compensating a phase error caused by the modulation of the dividing ratio; in the circuit of an embodiment of the disclosure, the means for compensating includes means for calculating an incremental value, indicative of an incremental phase error, according to the conversion factor and the modulation value, means for calculating a correction value accumulating the incremental value, and means for conditioning the control signal according to the correction value.

Fractional type phase-locked loop circuit with compensation of phase errors

A fractional-type phase-locked loop circuit is proposed for synthesizing an output signal multiplying a frequency of a reference signal by a fractional conversion factor, the circuit including means for generating a modulation value, means for generating a feedback signal dividing the frequency of the output signal by a dividing ratio, the dividing ratio being modulated according to the modulation value for providing the conversion factor on the average, means for generating a control signal indicative of a phase difference between the reference signal and the feedback signal, means for controlling the frequency of the output signal according to the control signal, and means for compensating a phase error caused by the modulation of the dividing ratio; in the circuit of an embodiment of the invention, the means for compensating includes means for calculating an incremental value, indicative of an incremental phase error, according to the conversion factor and the modulation value, means for calculating a correction value accumulating the incremental value, and means for conditioning the control signal according to the correction value.

Fractional-type phase-locked loop circuit with compensation of phase errors

A reading circuit for reading a datum stored in a storage material. In the reading circuit, a generating stage generates a read electrical quantity to be applied to the storage material, and a sensing stage is configured to generate an output electrical quantity that is indicative of a charge variation associated to the datum stored, and that occurs in the storage material due to application of the read electrical quantity; in particular, the sensing stage uses a charge-sensing amplifier electrically connected to the storage material.

Reading circuit and method in a data-storage system

An L-C resonant circuit with an adjustable resonance frequency, having a capacitor and a first inductor electrically coupled together and a second inductor magnetically coupled to the first inductor. Additionally, there is a control circuit to sense a signal representing a first current flowing through the first inductor and to force through the second inductor a second current that is a replica of the first current for setting the adjustable resonance frequency of the L-C resonant circuit.

Method of adjusting the resonance frequency of an L-C resonant circuit and resonant circuit

A phase-locked loop circuit is proposed for providing an output signal having a frequency depending on the frequency of a reference signal, the circuit including means for deriving a feedback signal from the output signal, means for providing a control signal indicative of a phase difference between the reference signal and the feedback signal, means for controlling the frequency of the output signal according to the control signal, and means for causing the circuit to enter a lock condition when the reference signal and the feedback signal have the same frequency and a pre-defined phase difference. In the circuit of an embodiment of the invention, the means for causing the circuit to enter the lock condition includes means for conditioning the control signal to have an instantaneous value substantially zero in the lock condition by means of a conditioning signal consisting of a series of pulses each one corresponding to the pre-defined phase difference.

Phase-locked loop circuit with current-pulse injection for improving linearity

An integrated amplifier may include a transconductance stage including a differential pair of input transistors of a first type of conductivity, respective resistive loads coupled to said input transistors, and a first bias circuit coupled to the input transistors. The first bias circuit may include a second differential pair of bias transistors having first conduction terminals coupled in common and second conduction terminals coupled to respective conduction terminals of the input transistors. The first bias circuit may also include respective second bias circuits coupled to the bias transistors to enable the input transistors in a conduction state with the input transistors being biased by a same respective bias current that flows through the respective input transistors. The first bias circuit may also include a capacitive network coupled to the bias transistors to define with the input transistors a feedback loop.

Low noise AC differential amplifier with reduced low corner frequency and current consumption

A phase difference detector adapted to generating a signal indicative of a phase difference between a first signal and a second signal, comprising: a first bistable element clocked by the first signal and having a first output signal, and a second bistable element clocked by the second signal and having a second output signal; means for determining the variation of the signal indicative of the phase difference, responsive to the first and second output signals, and a reset circuit having a first and a second inputs respectively connected to the first and second output signals and adapted to determine the resetting of the first and second bistable elements in response to the attainment of a respective prescribed state by the first and the second output signals. The first and second inputs of the reset circuit are substantially symmetrical to each other from the point of view of an input impedance associated to each of them.

Phase difference detector, particularly for a PLL circuit

A phase-locked loop circuit provides an output signal having a frequency depending on the frequency of a reference signal. The circuit includes a feedback circuit that derives a feedback signal from the output signal, a phase frequency detector that provides a control signal indicative of a phase difference between the reference signal and the feedback signal, a control circuit that controls the frequency of the output signal according to the control signal, and a conditioning circuit that conditions the control signal through a conditioning signal. The conditioning circuit includes a storage circuit that stores energy provided by the control signal and the conditioning signal during a first phase and transfers the accumulated energy to the control circuit during a second phase.

Phase-locked loop circuit with switched-capacitor conditioning of the control current

A fractional-type phase-locked loop circuit, for synthesizing an output signal multiplying a frequency of a reference signal by a selected fractional conversion factor, includes a frequency divider for generating a feedback signal dividing the frequency of the output signal by a frequency division factor selectable among at least two different integer-value division factors, and frequency divider control means for causing the frequency division factor to vary between the at least two integer-value division factors in a pre-defined number of cycles, thereby an average frequency division factor over said pre-defined number of cycles has a fractional value. Means are provided for compensating a phase error introduced by the frequency divider on the basis of a value indicative of the phase error obtained from said frequency divider control means. The phase-error compensation means includes rounding means, receiving an input binary code with a first number of binary digits, indicative of the phase error value, and providing an output binary code, with a second number of binary digits lower than the first number of digits, defining a rounded phase error value.

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Voghera, Italy

Guido Gabriele Albasini