Infineon Technologies Ag

Guenther Schindler

Manfred Engelhardt

Werner Pamler

Andreas Stich

Walter Hartner

Volker Weinrich

Zvonimir Gabric

Michael Schrenk

Markus Zundel

Frank S Hintermaier

Christine Dehm

Thomas Peter Haneder

Joachim Hoepfner

Peter Nelle

Wolfgang Hoenlein

Rainer Florian Schnabel

Harald Bachhofer

Eugen Unger

Barbara Hasler

Gabriela Brase

Gernot Steinlesberger

Martin Traving

Hans Cerva

Franz Winterauer

The invention relates to a semiconductor component comprising a semiconductor body, an insulation on the semiconductor body and a cell array arranged at least partly within the semiconductor body. The cell array has at least one p-n junction and at least one contact connection. The insulation is bounded in lateral direction of the semiconductor body by a circumferential diffusion barrier.

Chip edge sealing

An interconnect arrangement and fabrication method are described. The interconnect arrangement includes an electrically conductive mount substrate, a dielectric layer formed on the mount substrate, and an electrically conductive interconnect formed on the dielectric layer. At least a portion of the dielectric layer under the interconnect contains a cavity. To fabricate the interconnect arrangement, a sacrificial layer is formed on the mount substrate and the interconnect layer is formed on the sacrificial layer. The interconnect layer and the sacrificial layer are structured to produce a structured interconnect on the structured sacrificial layer. A porous dielectric layer is formed on a surface of the mount substrate and of the structured interconnect as well as the sacrificial layer. The sacrificial layer is then removed to form the cavity under the interconnect.

Interconnect arrangement and associated production methods

An MIM capacitor includes a first capacitor electrode, which is formed in the surface of a first intermediate dielectric, a second intermediate dielectric, which is formed on the first intermediate dielectric and has an opening that exposes the first capacitor electrode, and a first electrically conducting diffusion barrier layer, which is formed on the surface of the exposed first capacitor electrode. On the diffusion barrier layer and on the side walls of the opening there is also formed a capacitor dielectric and a second capacitor electrode on top.

MIM capacitor and associated production method

In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.

Method for manufacturing a layer arrangement and layer arrangement

A method for producing a layer arrangement is disclosed. A layer of oxygen material and nitrogen material is formed over a substrate that has a plurality of electrically conductive structures and/or over a part of a surface of the electrically conductive structures. The layer is formed using a plasma-enhanced chemical vapor deposition process with nitrogen material being supplied during the supply of silicon material and oxygen material by means of an organic silicon precursor material. The layer of oxygen material and nitrogen material is formed in such a manner that an area free of material remains between the electrically conductive structures. An intermediate layer including an electrically insulating material is formed over the layer of oxygen material and nitrogen material. A covering layer is selectively formed over the intermediate layer such that the area free of material between the electrically conductive structures is sealed from the environment and forms a cavity.

Plasma excited chemical vapor deposition method silicon/oxygen/nitrogen-containing-material and layered assembly

An interconnect arrangement () has a first layer (), a first layer surface (), thereon at least two interconnects () having a second layer surface () essentially parallel to the first layer surface (), thereon a respective second layer () for each interconnect (), the second layers () of adjacent interconnects covering regions between the adjacent interconnects (), and thereon a third layer (), which completely closes off the regions between the adjacent interconnects () by means of coverage.

Interconnect arrangement and method for fabricating an interconnect arrangement

A method for producing a ferroelectric layer includes preparing a substrate, applying a layer of material, which will be subsequently converted into the ferroelectric layer, and changing the material into the ferroelectric layer by applying an outer electrical field aligned with the direction desired in the ferroelectric material and heat treating the material. By providing a first noble metal electrode on the surface before applying the material that is to become the ferroelectric layer and then subsequently forming a second noble metal electrode on the ferroelectric layer, a ferroelectric storage capacitor can be formed. If the substrate is provided with memory cells, which include at least one transistor for each cell and the above-mentioned ferroelectric storage capacitors, a ferroelectric memory arrangement can be produced.

Method for producing a ferroelectric layer

A method is described for producing a conducting connection through insulating layers by way of a contact hole and conducting materials with which the contact hole is filled. The method permits the production of a contact hole resembling the shape of a wineglass, into which conducting filling material and barrier layers can be inserted without the known problems such as void formation, overetching trenches, and dielectric close-off. It is possible in this way, for example, to produce an electric connection between the diffusion zone of a selection transistor and the lower electrode of a storage capacitor of large-scale integrated DRAM and FeRAM components with the aid of only a few mask steps.

Method for producing an electrically conducting connection

The invention provides a semiconductor memory component with random access, also having a structure which is differentiated into memory cells and logic regions and has a lower oxide layer arranged on a silicon substrate and an upper oxide layer arranged on the lower oxide layer, each memory cell comprising at least one transistor in the transition region between silicon substrate and lower oxide layer and a capacitor in the transition region between lower oxide layer and upper oxide layer, which capacitor is connected to the transistor via a contact hole, which is filled with metal, in the lower oxide layer and comprises a ferroelectric arranged between two electrodes, the electrode which is connected to the transistor and adjoins the lower oxide layer having a relatively great thickness, and each logic region comprising at least one transistor in the transition region between silicon substrate and lower oxide layer, which transistor is connected to an electrode on the topside of the upper oxide layer via a contact hole, which is filled with metal, in the lower oxide layer and the upper oxide layer. According to the invention, it is provided that between the capacitors of the memory cells and the contact holes in the logic regions, level compensation between the topology of the memory cells and of the logic regions is created by dummy structures.

Semiconductor storage component with storage cells, logic areas and filling structures

The crystallization temperature of a ferroelectric layer ( ) (dielectric) for a storage capacitor can be lowered by applying a very thin (CeO layer ( ) to a first platinum electrode layer ( ) of the storage capacitor before the ferroelectric layer is deposited. The dielectric layer ( ) deposited in amorphous state is then crystallized by a temperature treatment step at a temperature in the range between 590&deg; C. and 620&deg; C. A second electrode layer ( ) is then applied to complete the storage capacitor.

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Munich, Germany

Guenther Schindler