Xilinx, Inc.

Guenter Stenz

Srinivasan Dasasathyan

Sudip K Nag

Rajat Aggarwal

Jason Helge Anderson

Grigor S Gasparyan

Parivallal Kannan

Victor Slonim

Mehrdad Eslami Dehkordi

Paul D Kundarewich

James L Saunders

Krishnan Anandh

Fan Zhang

Kamal Chaudhary

Satish B Sivaswamy

Anup Kumar Sultania

Garik Mkrtchyan

Nitin Deshmukh

Xiao Dong

Zhaoxuan Shen

Amish Pandya

Bhasker Pinninti

Ashot Shakhkyan

Examples described herein provide a non-transitory computer-readable medium storing instructions, which when executed on one or more processors, cause the one or more processors to perform operations. The operations include generating a plurality of child processes according to a number of a plurality of partitions in an integrated circuit (IC) design for an IC die, each of the plurality of child processes corresponding to and assigned to a respective one of the plurality of partitions. The operations include transmitting each of the plurality of partitions to a respective one of the plurality of child processes for routing, each of the plurality of partitions comprising a placement of components for the IC design. The operations include receiving a plurality of routings from the plurality of child processes. The operations include merging the plurality of routings into a global routing for the IC design by assembling together to form a global routing.

Distributed parallel processing routing

Disclosed approaches for processing a circuit design include interrupting processing of a circuit design by an electronic design automation (EDA) tool at a selected phase of processing. The tool serializes EDA state data into serialized state data while processing is interrupted and writes the serialized state data for subsequent restoration of tool state. To resume processing at the point of interruption, the EDA tool can read the serialized state data and deserialize the serialized state data. The EDA tool bypasses one or more phases of processing after reading the serialized state data and thereafter resumes processing of the circuit design.

Serialization in electronic design automation flows

Examples described herein provide a non-transitory computer-readable medium storing instructions, which when executed by one or more processors, cause the one or more processors to perform operations. The operations include: generating, using the one or more processors, a plurality of child processes according to a number of programmable dies of the multi-die device, each of the plurality of child processes corresponding to a respective programmable die of the multi-die device, wherein the plurality of child processes execute on different processors; partitioning a design for the multi-die device into a plurality of portions, each of the portions to be used to configure one of the programmable dies of the multi-die device; transmitting the plurality of portions of the design to the plurality of child processes for placement; and receiving placements from the plurality of child processes.

Multiprocessing flow and massively multi-threaded flow for multi-die devices

Disclosed approaches for processing a circuit design include providing access to checkpoint data of a design checkpoint of a circuit design and starting child processes by a parent process. An initial intermediate representation is generated by the parent process, and concurrent with the generating of the initial intermediate representation, the child processes load the checkpoint data into respective memory spaces. The parent process produces incremental updates to the design checkpoint. The parent process signals availability of the incremental updates to the child processes, which apply the incremental updates to the checkpoint data in the respective memory spaces. The child processes process the circuit design in response to completion of producing incremental updates by the parent placer process.

Incremental initialization by parent and child placer processes in processing a circuit design

Implementing a circuit design may include detecting, using computer hardware, a net of the circuit design with a hold timing violation, generating, using the computer hardware, a list including each load of the net, and filtering, using the computer hardware, the list based on predetermined criteria by, at least in part, removing each load from the list determined to be non-critical with respect to hold timing. Using the computer hardware, the circuit design is modified by inserting a flip-flop in the net to drive each load remaining on the list, clocking the flip-flop with a clock signal of a start point or an end point of a path traversing the net, and triggering the flip-flop with an opposite clock edge compared to the start point or the end point.

Timing optimizations in circuit designs using opposite clock edge triggered flip-flops

Vectorless dynamic power estimation for a circuit design may include forming, using a processor, a complex basic element within the circuit design, determining, using the processor, initial toggle rates for basic elements within the circuit design, and determining, using the processor, an initial toggle rate for the complex basic element. Vectorless dynamic power estimation further may include generating, using the processor, final toggle rates by updating the initial toggle rates according to a control signal analysis and calculating, using the processor, dynamic power dissipation for the circuit design using the final toggle rates.

Vectorless dynamic power estimation for sequential circuits

A method of placing input/output blocks on an integrated circuit device is described. The method may comprise receiving a circuit design having a plurality of input/output blocks to be placed at input/output sites of the integrated circuit device; modifying, for each input/output block of the circuit design, an input/output standard for the input/output block to include bus information; assigning, for each input/output block of the circuit design, an input/output site for the input/output block; and generating an input/output placement for the input/output blocks of the circuit design. A computer product is also disclosed.

Method of placing input/output blocks on an integrated circuit device

A computer-implemented method of implementing a circuit design within an integrated circuit (IC) can include, within an undirected graph representing the circuit design comprising nodes and edges, wherein each node represents a complex function block (CFB) or a pre-placed component of the circuit design and each edge represents at least one connection linking a pair of CFBs of the circuit design, determining an edge weight for each edge. The CFBs can be initially placed and a distance between each pair of CFBs joined by an edge of the undirected graph can be calculated. The CFB placement can be annealed by minimizing a cost function that calculates, for each edge, a product of the edge weight and the distance between the pair of CFBs joined by the edge. The cost function also can sum the products for each edge. The CFB placement can be stored.

Placing complex function blocks on a programmable integrated circuit

A method of assigning a plurality of input/output (I/O) objects of a circuit design to banks of a programmable integrated circuit (IC) using integer linear programming can include storing a plurality of constraints that depend upon a plurality of variables, wherein the plurality of constraints regulate assignment of each of the plurality of I/O objects to banks of the programmable IC (-), and storing a linear function that depends upon the plurality of constraints and a plurality of cost metrics, wherein each cost metric imposes a penalty when a selected I/O object of the circuit design is assigned to a bank of the programmable IC that is different from a bank to which the selected I/O object is assigned within a reference solution that is infeasible (). A result indicating whether a feasible solution exists for assignment of the plurality of I/O objects of the circuit design to banks of the target programmable IC can be determined by minimizing the linear function () subject to the plurality of constraints and outputting the result ().

Assignment of select input/output blocks to banks for integrated circuits using integer linear programming with proximity optimization

A method of input/output (I/O) block placement assigned to an input/output bank includes formulating a placement algorithm using integer linear programming (ILP) and simultaneously placing single groups and Relatively Placed Module (RPM) groups of I/O blocks in the I/O bank. The method further includes determining a placeability matrix P and a binary assignment matrix X used for the ILP. The method can further eliminate all assignment matrix elements of X equal to 0 in the integer linear programming and re-index any remaining elements. The method can further place all I/O blocks according to a solution if solving of the standard ILP formulation results in a feasible solution. Optionally, the method generates a placement solution that is as close as possible to an external reference solution specified by designer. Optionally, the method analyzes which constraints were violated and generates useful error information.

Placement of I/O blocks within I/O banks using an integer linear programming formulation

A method of creating relatively placed macros (RPMS) for a circuit design for a target device can include determining N best configurations for each of a plurality of connections of the circuit design, wherein each configuration specifies relative positioning of a source and a load of a connection and an estimated delay for the connection. The method can include calculating a maximum allowable delay for each of the plurality of connections of the circuit design and determining that a connection selected from the plurality of connections is critical according to the N best configurations associated with the critical connection and the maximum delay of the critical connection. A configuration from the N best configurations associated with the critical connection can be selected. An RPM for the critical connection can be generated using the selected configuration.

Methods of structured placement of a circuit design

Approaches for placing a plurality of input/output blocks (IOBs) of an electronic design in an integrated circuit are disclosed. The electronic design includes at least one input/output bus associated with a plurality of the IOBs, and the IOBs for each input/output bus are assigned to respective sets. For each combination of pairs of the sets a respective weight factor is generated to indicate a degree of coupling between the first and second sets in the electronic design. An order of the sets is generated, and the sets are placed in an ordered series of input/output sites in the integrated circuit according to the order of the sets. A cost function is evaluated for the pairs of the sets. The generating of the order of the sets and the placing of the sets is conditionally repeated responsive to the evaluating of the cost function.

Placement of input/output blocks of an electronic design in an integrated circuit

A method () of designing a programmable logic device can include the steps of identifying a cost function that penalizes floorplans of a circuit design that do not fit on the programmable logic device () and defining modules having components of a same type (). A set of shapes associated with a module can be determined (). The circuit design can be annealed () to determine a floorplan using the cost function and the set of shapes for the module.

Method system and apparatus for floorplanning programmable logic designs

A method of designing a programmable logic device can include receiving a modification to a programmable logic device that has been floorplanned. Modules of the programmable logic device that have been changed by the modification can be identified. The changed modules can be floorplanned thereby determining a placement solution that does not violate boundaries of unchanged modules. The programmable logic device then can be placed and routed.

Method, system, and apparatus for incremental design in programmable logic devices using floorplanning

Application of network flow techniques to constrained optimization problems is disclosed. The present of constrains may lead to infeasible solutions. The infeasible solutions can be removed by an iterative process of changing the structure of the network and/or the associated parameters. Specific applications of the invention to the placement of tristate buffers and clocks in integrated circuits are disclosed.

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Campbell, CA, United States of America

Guenter Stenz