International Business Machines Corporation

Guenter Mayer

Dieter F Wendel

Juergen Pille

Otto M Wagner

Christian Jacobi

Chung-Lung K Shum

Eric M Schwarz

William Vincent Huott

Michael H Wood

Martin Eckert

Rolf Sautter

Hans-Werner Tast

Wilhelm Ernst Haller

Timothy Gerard McNamara

Ulrich Krauch

Sean Michael Carey

Stefan Buettner

Thomas Froehnel

A method to generate a magnitude result of a mathematic operation of two decimal operands within one cycle in a decimal arithmetic logic unit structure, wherein the decimal operands are in hexadecimal sign magnitude format.

Method and decimal arithmetic logic unit structure to generate a magnitude result of a mathematic

A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times itscommencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.

Generating a local clock domain using dynamic controls

A circuit () combining level shift function with gated reset is described, performing a simple logic function with inputs supplied from a lower voltage (VD) and a drive out at its output () with a higher voltage (VC). Said circuit () comprises a gated reset scheme plus devices () for logic function.

Circuit combining level shift function with gated reset

A device and method for storing information including an array of memory cells organized in bitlines and wordlines. The bitlines are subdivided in sections of wordlines and the sectioned bitlines are connected to a global bitline by a connector. The connector is made bidirectional and uses the high order part of the wordline addresses for this section of bitlines as a disable reset command. The reset stays active for unselected portions, compensating leakage of a mass of unselected cells which could disturb valid read signals.

Device for storing information and a method for partial write and restore

The invention describes a high-performance static logic compatible multiport latch. The latch is controlled by at least a first and a second clock (CLK , CLK ), which consist of at least first and second data input ports ( ) with together at least three data inputs (DATA , . . . , DATA DATA , . . . , DATA ) and at least one data output (OUT). The first clock (CLK ) controls whether data (DATA , . . . , DATA ) applied to the first data input ports ( ) is stored in or clocked through the latch ( ), the second clock (CLK ) controls whether data (DATA , . . . , DATA ) applied to the second data input ports ( ) is stored in or clocked through the latch, and either the first clock (CLK ) or the second clock (CLK ) clocks data into the latch at the same time.

Static logic compatible multiport latch

The present invention relates to storage devices and in particular, it relates to a method for testing the storage quality of history dependent memory array cells. A cell can be stressed selectively with predetermined test conditions such that these test conditions cover all of the hardware status distribution which might arise when the cell is operated under the full range of operating conditions. This is basically achieved by cutting off a predetermined cutoff width of the trailing edge of the active wordline select pulse.

SOI array sense and write margin qualification

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Schoenaich, Germany

Guenter Mayer