Intel Corporation

Gudbjorg H Oskarsdottir

Daoqiang Lu

Eric Jin Li

James Chris Matayabas, Jr

Paul A Koning

Christopher L Rumer

Tiffany Byrne

Darcy E Fleming

Mitesh C Patel

Sujit Sharan

Ashay A Dani

Mukul P Renavikar

Chris Matayabas

Chris Rumer

Beverly J Canham

Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability.

Semiconductor wafer coat layers and methods therefor

According to one aspect of the invention, a polymer device and a method of constructing a polymer device are provided. The polymer device includes a first conductor, a second conductor, and a polymeric body between the first and second conductors. The polymeric body includes a polymer material and a phyllosilicate material.

Polymer device with a nanocomposite barrier layer

An embodiment of the invention reduces damage caused to a polymer ferroelectric layer in a polymer ferroelectric memory device by creating excess holes in the insulating metal nitride and/or metal oxide layers between the metal electrodes and polymer ferroelectric layer. The excess holes in the metal nitride and/or metal oxide trap electrons injected by the metal electrodes under AC bias that would otherwise damage the polymer ferroelectric layer.

Polymer memory device with electron traps

Numerous embodiments of an apparatus and method to stress and warpage of semiconductor packages are described. In one embodiment, a semiconductor die is disposed above a substrate. An encapsulating material is disposed above the substrate and semiconductor die, in which the encapsulating material has a combination of a low coefficient of thermal expansion material and a high coefficient of thermal expansion material.

Package stress management

A silicon wafer has a plurality of integrated circuits terminated on a surface of the silicon wafer. The silicon wafer has a soluble protective coat on the surface of the silicon wafer. The coated silicon wafer may be processed by laser scribing. A solvent wash may be used to remove the soluble protective coat and debris from laser scribing. The coated silicon wafer may be saw cut after laser scribing. A flow of solvent may be provided during the saw cutting. The flow of solvent may be sufficient to remove at least a substantial portion of the soluble protective coat.

Silicon wafer with soluble protective coating

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Chandler, AZ, United States of America

Gudbjorg H Oskarsdottir