Texas Instruments Corporation

Guatam V Thaker

Daty Michael Rogers

A process for forming a polysilicon line having linewidths below 0.35 .mu.m. The layer of polysilicon (20) is deposited over a semiconductor body (10). A layer of bottom anti-reflective coating (BARC) (30) is deposited over the polysilicon layer (20). A resist pattern (40) is formed over the BARC layer (30) using conventional lithography (e.g., I-line lithography). The resist pattern (40) has minimum dimensions of 0.30 .mu.m or greater. The BARC layer (30) is etched using the resist pattern (40) until the endpoint is detected. The BARC layer (30) and resist pattern (40) are then overetched using an isotropic etch having a selectivity of one-to-one between the BARC and resist. The overetch is a timed etch to control the linewidth reduction in the resist/BARC pattern. The minimum dimension of the pattern (50) is reduced to below 0.3 .mu.m. Finally, the polysilicon layer (20) is etched using the reduced width pattern (50).

Growing community of inventors

Plano, TX, United States of America

Guatam V Thaker