Leland Stanford Junior University

Pdf Solutions, Incorporated

Guanyuan Michael Yu

Brian E Stine

Eric Perozziello

Senthil Arthanari

Spencer B Graves

Marci Yi-Ting Liao

Anand Inani

Michael V Williamson

In one embodiment, wafers are processed to build test structures in the wafers. The wafers may be processed in tools of process steps belonging to a process module. The test structures may be tested to obtain defectivity data. Tool process parameters may be monitored and collected as process tool data. Other information about the wafers, such as metrology data and product layout attribute, may also be collected. A model describing the relationship between the defectivity data and process tool data may be created and thereafter used to relate the process tool data to a yield of the process module. The model may initially be an initial model using process tool data from a limited number of test wafers that contain test structures. The model may also be an expanded model using process tool data from product wafers containing embedded test structures in areas with no product devices.

Identifying yield-relevant process parameters in integrated circuit device fabrication processes

Currently semiconductor processing and device manufacturing relies heavily on continued scaling of critical dimensions for cost reduction and performance enhancement. In order to continue this scaling below 0.1 micron with acceptable manufacturing yields, reliable measurement of electrical charge distribution and the placement of dopants is essential, yet no conventional technique exists to obtain distortion-free cross-sectional images. An aspect of the invention relates to a technique for forming a precisely-located, substantially atomically smooth cross-section of a crystalline sample suitable for Scanning Capacitance Microscopy analysis. Another aspect of the invention provides a method for deconvolving Scanning Capacitance raw data into an accurate representation of electrical carrier distributions suitable for the higher resolution attainable with the new sample preparation technique.

Scanning capacitance sample preparation technique

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San Jose, CA, United States of America

Guanyuan Michael Yu