Shanghai Huali Microelectronics Corporation

Guanqun Huang

Hua Shao

Haoyu Chen

Tianzhi Zhu

Xiaohua Ju

Li He

Shaokang Yao

The application provides a SCR and a manufacturing method thereof. The SCR comprises: a P-type heavily doped regionand an N-type lightly doped regionforming an anode formed on the upper part of an N-type well, a P-type heavily doped regionand an N-type heavily doped regionforming a cathode formed on the upper part of a P-type well, an active region of the N-type wellis between the N-type lightly doped regionand an interface of the N-type welland the P-type well, a STI is provided between the N-type heavily doped regionand the interface, the STI is adjacent to the N-type heavily doped region, and an active region of the P-type wellis provided between the STI and the interface. The present application can improve trigger voltage of the SCR and save layout area.

No-snapback silicon controlled rectifier and method for making the same

The application provides a SCR and a manufacturing method thereof. The SCR comprises: a P-type heavily doped regionand an N-type heavily doped regionforming an anode formed on the upper part of an N-type well, a P-type heavily doped regionand an N-type heavily doped regionforming a cathode formed on the upper part of a P-type well, an active region of the N-type wellis between the N-type heavily doped regionand an interface of the N-type welland the P-type well, a STI is provided between the N-type heavily doped regionand the interface, the STI is adjacent to the N-type heavily doped region, and an active region of the P-type wellis provided between the STI and the interface. The present application can improve trigger voltage of the SCR and save layout area.

Silicon controlled rectifier and method for making the same

Embodiments described herein relate to a method for fabricating word lines of a NAND memory. In the process for fabricating the word lines of the NAND memory, by adding a sacrificial pattern at a position close to a core layer or a sidewall of a select transistor at the edge of the word lines, the actual word line pattern is not at the outermost edge of the pattern, the pattern density of the edge word line pattern is closer to the pattern density of the middle word line pattern, the morphology and size of the edge word line are closer to the morphology and size of the middle area during core layer etching and sidewall etching, and thus the uniformity of the finally etched word lines is improved.

Method for fabricating word lines of NAND memory and NAND memory comprising word lines fabricated by adopting the same

The present invention provides a method for optimizing a critical dimension for double patterning for NAND flash, forming a core oxide layer on amorphous silicon layer on substrate; densifying the core oxide layer and etching it to form a core pattern; measuring CD values of the bottom and top of the core pattern; providing etching rates of a non-densified core oxide layer and a densified core oxide layer under the same etching condition; calculating the thickness of the core oxide layer required to be densified according to the CD values of the bottom and top of the core pattern and the etching rates to determine the densifying time. The present invention precisely controls the morphology and CD, and obtains a double-patterned target pattern with consistent CD sizes of a top and a bottom and a consistent bottom height, so as to improve a product yield.

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Shanghai, China

Guanqun Huang