Intel Corporation

University System of Maryland

Washington University

Government of the United States of America, As Represented by the Secretary of Commerce

George Mason University

Guannan Liu

Mark Armstrong

Bernhard Sell

Akm A Ahsan

Hyung-Jin Lee

Albert V Davydov

Mona Zaghloul

Saurabh Morarka

Abhishek Motayed

Geetha Aluri

Vladimir P Oleshko

Ritu Bajpai

Qiang Yu

Mulpuri V Rao

Said Rami

Ratan Debnath

Brian Thomson

Ting Xie

Baomei Wen

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.

Planar buried channel structure integrated with non-planar structures

Buried channel structure integrated with non-planar structures

Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.

Field-effect transistors with asymmetric gate stacks

A dual mode snap back circuit device is disclosed. The dual mode snap back device may be used for electrostatic discharge (ESD) protection, and may provide both positive ESD protection and negative ESD protection. The dual mode snap back device may implement both an n-type metal-oxide-semiconductor (NMOS) transistor (e.g., a gate-grounded NMOS transistor, such as a gate-grounded extended drain NMOS (GGEDNMOS) transistor) to provide protection against positive ESD events and a bipolar junction transistor (BJT) (e.g., a PNP BJT) to provide protection against negative ESD events. Other embodiments may be described and claimed.

Dual mode snap back circuit device

A nanostructure sensing device comprises a semiconductor nanostructure having an outer surface, and at least one of metal or metal-oxide nanoparticle clusters functionalizing the outer surface of the nanostructure and forming a photoconductive nanostructure/nanocluster hybrid sensor enabling light-assisted sensing of a target analyte.

Highly selective nanostructure sensors and methods of detecting target analytes

Growing community of inventors

Portland, OR, United States of America

Guannan Liu