Csmc Technologies Fab2 Co., Ltd.

Csmc Technologies Fab1 Co., Ltd.

Guangtao Han

Guipeng Sun

Feng Huang

Feng Lin

Longjie Zhao

Bing Zhao

Huatang Lin

Shu Zhang

Liangliang Ping

Fengying Chen

Lixiang Liu

Provided are a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: providing a wafer on which a first N well (), a first P well () and a channel region shallow trench isolating structure () are formed; forming a high-temperature oxidation film on the surface of the wafer by deposition; photoetching and dryly etching the high-temperature oxidation film, and reserving a thin layer as an etching buffer layer; performing wet etching, removing the etching buffer layer in a region which is not covered by a photoresist, and forming a mini oxidation layer (); performing photoetching and ion injection to form a second N well () in the first N well and form a second P well () in the first P well; forming a polysilicon gate () and a gate oxide layer on the surface of the wafer; and photoetching and injecting N-type ions to form a drain electrode () and a source electrode ().

Laterally diffused metal oxide semiconductor field-effect transistor and manufacturing method therefor

The present invention relates to a junction field effect transistor. The junction field effect transistor comprises a substrate (), a buried layer in the substrate, a first well region () and a second well region () that are on the buried layer, a source lead-out region (), a drain lead-out region (), and a first gate lead-out region () that are in the first well region (), and a second gate lead-out region () in the second well region (). A Schottky junction interface () is disposed on the surface of the first well region (). The Schottky junction interface () is located between the first gate lead-out region () and the drain lead-out region (), and is isolated from the first gate lead-out region () and the drain lead-out region () by means of isolation structures. The present invention also relates to a manufacturing method for a junction field effect transistor.

Junction field effect transistor and manufacturing method therefor

The present invention relates to a method for manufacturing a laterally insulated-gate bipolar transistor, comprising: providing a wafer having an N-type buried layer (), an STI (), and a first N well ()/a first P well () which are formed successively from above a substrate; depositing and forming a high-temperature oxide film on the first N well () of the wafer; performing thermal drive-in on the wafer and performing photoetching and etching on the high-temperature oxide film to form a mini oxide layer (); performing photoetching and ion implantation so as to form a second N well () inside the first N well () and second P wells () inside the first N well () and the first P well (); then successively forming a gate oxide layer and a polysilicon gate (), wherein one end of the gate oxide layer and the polysilicon gate () extends onto the second P well () inside the first N well (), and the other end extends onto the mini oxide layer () on the second N well (); and photoetching and injecting N-type ions between the mini oxide layer () and the STI () adjacent to the mini oxide layer () to form a drain electrode, and at the same time forming a source electrode () inside the second P well ().

Method for manufacturing laterally insulated-gate bipolar transistor

Provided is a manufacturing method for a laterally diffused metal oxide semiconductor device, comprising the following steps: growing an oxide layer on a substrate of a wafer (S); coating a photoresist on the surface of the wafer (S); performing photoetching by using a first photoetching mask, and exposing a first implantation window after development (S); performing ion implantation via the first implantation window to form a drift region in the substrate (S); coating one layer of photoresist on the surface of the wafer again after removing the photoresist (S); performing photoetching by using the photoetching mask of the oxide layer of the drift region (S); and etching the oxide layer to form the oxide layer of the drift region (S). Further provided is a laterally diffused metal oxide semiconductor device.

Laterally diffused metal oxide semiconductor device and manufacturing method therefor

A lateral double diffused metal oxide semiconductor field-effect transistor includes semiconductor substrates, body regions positioned in the semiconductor substrates, drift regions positioned in the semiconductor substrates, source regions and a body leading-out region which are positioned in the body regions and spaced from the drift regions, a field region and drain regions which are positioned in the drift regions, and gates positioned on the surfaces of the semiconductor substrates to partially cover the body regions, the drift regions and the field region, wherein the field region is of a finger-like structure and comprises a plurality of strip field regions which extend from the source regions to the drain regions and are isolated by the active regions; and the strip field regions provided with strip gate extending regions extending from the gates.

Lateral double diffused metal oxide semiconductor field-effect transistor

The present invention discloses a high voltage JFET. The high voltage JFET includes a second conductivity type drift region located on the first conductivity type epitaxial layer; a second conductivity type drain heavily doped region located in the second conductivity type drift region; a drain terminal oxygen region located on the second conductivity type drift region and at a side of the second conductivity type drain heavily doped region; a first conductivity type well region located at a side of the second conductivity type drift region; a second conductivity type source heavily doped region and a first conductivity type gate heavily doped region located on the first conductivity type well region, and a gate source terminal oxygen region; a second conductivity type channel layer located between the second conductivity type source heavily doped region and the second conductivity type drift region; a dielectric layer and a field electrode plate located on the second conductivity type channel layer. Wherein a drain electrode electrically is led out from the second conductivity type drain heavily doped region; a source electrode electrically is led out from a connection of the field electrode plate and the second conductivity type source heavily doped region; and a gate electrode electrically is led out from the first conductivity type gate heavily doped region. The transistor has a high breakdown voltage and easy to be integrated.

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Jiangsu, China

Guangtao Han