Western Digital Technologies, Inc.

Ngd Systems, Inc.

S-tec Corporation

Skyera, LLC

Morpho Technologies

Guangming Lu

Kent Douglas Anderson

Anantha Raman Krishnan

Shafa Dahandeh

Leader Ho

Andrew John Tomlin

Mark Moshayedi

Joao Alcantara

Vladimir Alves

Ricardo Cassia

Kamyar Souri

Radoslav Danilak

Dengtao Zhao

Rodney Norman Mullendore

Justin Cree Jones

Shayan Srinivasa Garani

Jimmy C Pu

An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. Bit patterns provided by multiple reads of reference memory locations can be counted and used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.

Method and system for decoding data based on association of first memory location and second memory location

Soft-decision input generation for data storage systems

An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. 0-to-1 and 1-to-0 bit flip count data provided by multiple reads of reference memory locations can be used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.

Data storage system and method for decoding data based on extrapolated flipped-bit data

A system and method for long term data retention in a flash memory. In some embodiments, the method includes transitioning the flash memory to a long term data retention state by re-storing first encoded data, the first encoded data being initially stored in the flash memory at a first code rate. The re-storing may include determining a second code rate, lower than the first code rate; reading the first encoded data from the flash memory; decoding the first encoded data at the first code rate to obtain first decoded data; encoding the first decoded data at the second code rate to form second encoded data; and storing the second encoded data in the flash memory.

SSD for long term data retention

A system and method for adaptive multiple read of NAND flash memory. A solid state drive may employ adaptive multiple-read to perform enhanced performance error correction using soft decisions without a performance penalty that otherwise might result from performing unnecessary reads. The soft decision error correcting algorithm may employ lookup tables containing log likelihood ratios. The method may include performing one or more read operations to obtain one or more raw data words for a code word, attempting to decode the code words using the one or more raw data words, and performing additional read operations when the decoding attempt fails. This process may be repeated until a decoding attempt succeeds.

System and method for adaptive multiple read of NAND flash

A system and method for providing consistent performance in a storage device, such as a solid state drive. A threshold value for command execution time for a command in a category of command (e.g., a read command or a write command) and a command size, is stored in the storage device. When a host command in the category (e.g., a read command) and corresponding size is received, the storage device executes the command, and if it completes execution of the command in a time that is less than the threshold value, the solid state drive waits until an amount of time equal to the threshold value has elapsed before sending the command completion.

System and method for consistent performance in a storage device

A data storage system configured to adaptively code data is disclosed. In one embodiment, a data storage system controller determines a common memory page size, such as an E-page size, for a non-volatile memory array. Based on the common memory page size, the controller selects a low-density parity-check (LDPC) code word length from a plurality of pre-defined LDPC code word lengths. The controller determines LDPC coding parameters for coding data written to or read from the memory array based on the selected LDPC code word length. By using the plurality of pre-defined LDPC code word lengths, the data storage system can support multiple non-volatile memory page formats, including memory page formats in which the common memory page size does not equal any LDPC code word length of the plurality of pre-defined LDPC code word lengths. Flexibility and efficiency of data coding can thereby be achieved.

Adaptive error correction codes for data storage systems

A system and method for generating lookup tables for use in an adaptive multiple-read system for reading flash memory. Successive different attempts are made to decode previously stored data using error correction codes, the attempts differing, for example, with respect to the combination of raw data words used for each attempt, each raw data word having been obtained by reading a code word of data using a different word line voltage. When a decoding attempt succeeds, log likelihood ratios are calculated from counts of flipped bits, i.e., bits in the raw data read from the memory having a different value than the corresponding bits in the decoded data.

Flash channel calibration with multiple lookup tables

A method of restoring user data in a modular solid-state drive including memory channels coupled to respective ones of non-volatile memory cards, the method including: upon physical replacement of a defunct memory card of the non-volatile memory cards with a new non-volatile memory card, and power on of the modular solid-state drive, retrieving a firmware segment and a system segment of the modular solid-state drive from unaffected memory channels of the memory channels not coupled to the new non-volatile memory card; rebuilding a firmware of the modular solid-state drive based on the retrieved firmware segment; rebuilding a data mapping table associated with the non-volatile memory cards based on the retrieved system segment; and restoring full integrity of the user data originally stored on the non-volatile memory cards based on the rebuilt data mapping table and data from the unaffected memory channels.

Method of channel content rebuild in ultra-high capacity SSD

Embodiments of decoders having early decoding termination detection are disclosed. The decoders can provide for flexible and scalable decoding and early termination detection, particularly when quasi-cyclic low-density parity-check code (QC-LDPC) decoding is used. In one embodiment, a decoder iteratively decodes a data unit using a decoding matrix comprising a plurality of layers. After at least one iteration of decoding the data unit, the decoder determines whether the decoded data unit from a completed iteration and one or more layers of the plurality of layers satisfy a parity check equation. In response to determining that the decoded data unit from the completed iteration and each layer of the plurality of layers satisfy the parity check equation, the decoder terminates decoding the data unit. Advantageously, the termination of decoding of the data unit can reduce a number of iterations performed to decode the data unit.

Decoder having early decoding termination detection

Embodiments of solid-state storage devices provided herein include a voltage threshold calculation mechanism to calculate an optimal voltage read threshold for minimizing read errors. The system may be configured to determine optimal reference voltage value(s) by interpolating a pair of reads at two different threshold levels to determine the point that generates the least number of errors. In some cases, the evaluation may be an approximation based on a Cumulative Distribution Function (CDF) of errors of a first type and a second type. In other cases, the evaluation may be a calculation of an optimal voltage threshold based on the CDF of the errors. In yet other cases, the evaluation may be based on the Probability Density Function (PDF) of the errors.

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Irvine, CA, United States of America

Guangming Lu