Sandisk Technologies Inc.

Guangle Zhou

Tanmay Kumar

Ming-Che Wu

Christopher John Petti

Yung-Tin Chen

Juan Pablo Saenz

Abhijit Bandyopadhyay

Yangyin Chen

Perumal Ratnam

Chuanbin Pan

Deepak Kamalanathan

Yubao Li

A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and conductive oxide material layer, forming a first barrier material layer between the word line and the nonvolatile memory material, forming a second barrier material layer between the bit line and the nonvolatile memory material, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line.

Methods and apparatus for three-dimensional nonvolatile memory

A matrix rail structure is formed over a substrate. The matrix rail structure includes a pair of lengthwise sidewalls that extend along a first horizontal direction and comprises, or is at least partially subsequently replaced with, a set of at least one gate electrode rail extending along the first horizontal direction and straight-sidewalled gate dielectrics. A pair of vertical semiconductor channel strips and a pair of laterally-undulating gate dielectrics can be formed on sidewalls of the matrix rail structure for each vertical field effect transistor. At least one laterally-undulating gate electrode extending along the first horizontal direction is formed on the laterally-undulating gate dielectrics. Bottom active regions and top active regions are formed at end portions of the vertical semiconductor channel strips. The vertical field effect transistors can be formed as a two-dimensional array, and may be employed as access transistors for a three-dimensional memory device.

Multi-gate vertical field effect transistor with channel strips laterally confined by gate dielectric layers, and method of making thereof

A resistive memory device includes a first electrode, a sidewall spacer electrode located on a sidewall of a dielectric material contacting the first electrode, a resistive memory cell containing a resistive memory material and contacting the sidewall spacer electrode, and a second electrode containing the resistive memory cell.

Resistive memory device having sidewall spacer electrode and method of making thereof

A method is provided that includes forming a dielectric material above a substrate, forming a hole in the dielectric material, the hole disposed in a first direction, forming a word line layer above the substrate via the hole, the word line layer disposed in a second direction perpendicular to the first direction, the word line layer including a first conductive material having a first work function, forming a nonvolatile memory material on a sidewall of the hole, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, forming a local bit line in the hole, the local bit line including a second conductive material having a second work function, wherein the first work function is greater than the second work function, and forming a memory cell comprising the nonvolatile memory material at an intersection of the local bit line and the word line layer.

A multiple junction thin film transistor (TFT) is disclosed. The body of the TFT may have an n+ layer residing in a p&#x2212; region of the body. The TFT may have an n+ source and an n+ drain on either side of the p&#x2212; region of the body. Thus, the TFT has an n+/p&#x2212;/n+/p&#x2212;/n+ structure in this example. The n+ layer in the p&#x2212; region increases the breakdown voltage. Also, drive current is increased. The impurity concentration in the n+ layer in the p&#x2212; body and/or thickness of the n+ layer in the p&#x2212; body may be tuned to increase performance of the TFT. In an alternative, the body of the TFT has a p+ layer residing in an n&#x2212; region of the body. The TFT may have a p+ source and a p+ drain on either side of the p&#x2212; region of the body.

Multiple junction thin film transistor

A method is provided that includes forming a first vertical bit line disposed in a first direction above a substrate, forming a first word line disposed in a second direction above the substrate, the second direction perpendicular to the first direction, forming a first memory cell comprising a nonvolatile memory material at an intersection of the first vertical bit line and the first word line, forming a transistor above the substrate, and forming a first bit line select device coupled between the first vertical bit line and the transistor.

Methods and apparatus for vertical bit line structures in three-dimensional nonvolatile memory

A first patterned stack and a second patterned stack are formed over a substrate, each of which includes a bottom semiconductor layer, a bottom dielectric spacer layer, a conductive material layer, and a top dielectric spacer layer. Gate dielectrics and vertical semiconductor portions are sequentially formed on each patterned stack. Vertical semiconductor portions are removed from around the second patterned stack, while masked around the first patterned stack. Electrical dopants are introduced to top regions and bottom regions of the remaining vertical semiconductor portions to form a vertical switching device that includes the first patterned stack, while the second patterned stack functions as a horizontal interconnect structure. The vertical switching device can be a transistor or a gated diode.

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San Jose, CA, United States of America

Guangle Zhou