Wuhan China Star Optoelectronics Technology Co., Ltd.

Guanghui Hong

Qiang Gong

Jingfeng Xue

Gui Chen

Chunqian Zhang

A display panel is disclosed. The display panel includes a de-multiplexing switch group, a signal transmission line, a first control line, and a second control line. The first control line and the second control line are connected to the de-multiplexing switch group. Voltage levels of signals of the first control line and the second control line are opposite to each other, and a number of groups of the first control line and the second control line which intersect the signal transmission line is greater than or equal to zero. Pictures of display panels can be prevented from being affected by intersections of lines.

Display panel

A TFT array panel includes a primary display area and a slitting-edge display area. In the slitting-edge display area, a first metallic routing layer includes a first data line and a second metallic routing layer includes a first gate line. The first data line is connected to the second metallic routing layer through a hole in the interlayer dielectric layer so that the first data line overlaps the first gate line to form an overlapping capacitance to compensate for a gate line RC value.

Thin film transistor array panel and display device

An array substrate and a display panel are disclosed. The array substrate includes: a GOA unit; a plurality of gate lines, electrically connected to the GOA unit; and a static-conducting device, electrically connected between the plurality of gate lines, in such a way that the plurality of gate lines are electrically connected to each other. In the array substrate, the static-conducting device is arranged between the plurality of gate lines, in such a way that the plurality of gate lines are electrically connected to each other to together resist the ESD. In this way, the anti-electrostatic discharge ability of the array substrate is improved, and the product quality is also improved.

Array substrate and display panel

A thin film transistor array substrate and a display apparatus are disclosed. The thin film transistor array substrate includes a number of scan lines, data lines and pixel units. Each of the pixel units includes a thin film transistor and a pixel electrode. The thin film transistor includes a gate electrode, a source electrode and a drain electrode. The gate electrode is electrically connected to one of the scan lines, the source electrode is electrically connected to one of the data lines, and the drain electrode is electrically connected to the pixel electrode. The source electrode is arranged in a same layer as the data lines while the drain electrode and the source electrode are respectively arranged in different layers. Therefore, the implementation of the present disclosure may augment the PPI (Pixel units per Inch) of display apparatus without reducing its aperture ratio and product yield ratio.

Thin film transistor array substrate and display apparatus

The disclosure provides a display panel, a method for making the display panel, and a method for controlling the display panel. The display panel comprises: multiple gate lines and multiple data line crossing the multiple gate lines to form multiple pixel regions; multiple pixel electrodes in the multiple pixel regions; multiple first thin film transistors in the multiple pixel regions, the gates of the multiple first thin film transistors are connected to the gate lines, and the sources and the drains are connected to the data lines and the pixel electrodes respectively; and a second thin film transistor between and connecting two adjacent pixel electrodes, wherein the second thin film transistor is in a non-conducting state when the display panel is under normal operation, and the second thin film transistor is in a conducting state when the display panel is under a power failure condition.

Display panel, method for making the same and method for controlling the same

A circuit and method for detecting pixel potential of a display panel and a display panel is provided. The circuit comprises a multiplexed output selector, at least one detection circuit and at least one signal amplifier. The detection circuit comprises a first TFT receiving a test signal and being connected to the multiplexed output selector. The multiplexed output selector is configured to selectively conduct the first data line, which is connected to a currently-detected sub-pixel unit, to the first TFT in accordance with a reverse clock signal to transmit a pixel potential signal of the currently-detected sub-pixel unit to the first TFT to control the first TFT to transmit the test signal to the signal amplifier. The signal amplifier is configured to receive and amplify the test signal to obtain and output a received signal. The present disclosure is able of measuring real pixel potential of the display panel.

Circuit and method for detecting pixel potential of a display panel, and a display panel

A GOA circuit includes an output module in which a second TFT is arranged. The second TFT has a drain connected to a source of a first TFT, a gate receiving a first control signal, and a source receiving an Mth clock signal. The first control signal controls the second TFT to turn on and off. Alternatively, the drain of the second TFT is connected to the source of the first TFT, the gate receiving the Mth clock signal and the source connected to the first node to allow the second TFT to be conducted on only when the Mth clock signal is a high voltage and the first node is of a high voltage and is cut off at the remaining time. It is possible to prevent a voltage difference from being induced between the source and drain of the first TFT to reduce the electric current stress.

Goa circuit

The present application provides an NMOS type GOA circuit including: M cascaded GOA units, a Nth level GOA unit including: a forward reverse scan control circuit, a node signal control circuit, a node signal output circuit, a pull down circuit, and a output circuit; the forward reverse scan control circuit configured to perform a forward scan or a reverse scan according to a forward scan control signal or a reverse scan control signal; the output circuit including a first thin film transistor and a second thin film transistor, the node signal output circuit including a third thin film transistor, and the pull-down circuit including a fourth thin film transistor; wherein M&#x2265;N&#x2265;1, the high potential signal is a direct current signal, and the first and the drain terminal of the thin film transistor is one of a source and a drain, and the drain, the third terminal is a gate.

NMOS type GOA circuit and display panel

An array test circuit is provided. The circuit includes: at least one first demultiplexer module, an enable signal input point, a plurality of measurement and control signal input points, a plurality of data lines, a plurality of enabling switches, a plurality of anti-floating switches, and an inverter. A control terminal of each anti-floating switch is electrically connecting to an inverted enable signal, an input terminal is accessed to an OFF signal of the measurement and control switch, an output terminal is electrically connected to a corresponding measurement and control signal input point. The anti-floating switch can be turned on and input the OFF signal to the measurement and control signal input point when the liquid crystal panel is displayed, it can ensure the demultiplexing switches are kept in OFF state, preventing the switches in floating state and improving the working stability of the liquid crystal display panel.

Array test circuit

A method for manufacturing an array substrate and an array substrate are provided, which include a first insulating for forming a gate, a scan line, a first data line, and a second data line of the thin film transistor, wherein the first data line and the second data line are located near both sides of the scan line, and are not electrically connected with the scan line, and a second insulating layer for forming a source, a drain, a connecting line, and a touch signal line of the thin film transistor, wherein the connecting line is configured to electrically connect the first data line with the second data line.

Method for manufacturing array substrate and array substrate

The present disclosure provides a gate driver on array (GOA) circuit, where the GOA circuit includes a GOA driving chip, a GOA driving signal line, an array substrate test chip, a test signal line, and a GOA protecting circuit. The GOA driving chip is used to generate a scan driving signal. The GOA driving signal line is used to transmit the scan driving signal to a corresponding scan line. The array substrate test chip is used to generate an array substrate test signal. The test signal line is used to transmit the array substrate test signal to the corresponding scan line. The GOA protecting circuit is arranged between the GOA driving signal line and the test signal line.

Gate driver on array circuit and LCD panel having GOA protecting circuit

The present invention provides an array substrate and an repairing method thereof, wherein the array substrate includes adjacent two level GOA unit circuits, wherein an output terminal of a Nth level GOA unit circuit is connected to a Nth level gate line, an output terminal of a N+1th level GOA unit circuit is connected to a N+1th level gate line; and a repairing structure disposed between the Nth level gate line and the N+1th level gate line, the repairing structure configured to turn on the Nth level gate line and the N+1th level gate line by melting when the Nth level GOA unit circuit or the N+1th level GOA unit circuit damaged. A repairing structure is added between two adjacent gate lines, when a certain GOA unit circuit is damaged, the repairing structure is melted by a laser to make the adjacent two gate lines communicate with each other.

Array substrate and repairing method thereof

A gate driver on array (GOA) circuit of the present disclosure includes a current leakage limiting module. The current leakage limiting module limits current leakage of a first node to maintain a high level of the first node when an embedded touch display panel enters a stage in which signal interruption occurs and touch scanning is performed, further reducing risk of cascade failure and making the GOA circuit stable.

Gate driver on array circuit

The present application provides a demux control circuit. The demux control circuit includes a driving chip, a logic circuit, and a demux for providing two or three pulse signals to the logic circuit, the logic circuit including a plurality of NOR Gate and a plurality of buffers which can convert two pulse signals into three control signals or convert the three pulse signals into four control signals through the cooperation of the NOR gates and the buffers to achieve outputting a larger number of control signals by a smaller number of pins, thereby reducing the number of pins outputted from the driving chip and reduce production costs.

Demux control circuit

The disclosure discloses a flat panel display device and a scan driving circuit thereof. The scan driving circuit includes a plurality of first scan drivers and a plurality of second scan drivers that are cascaded, the plurality of first scan drivers and the plurality of second scan drivers receive a clock signal alternately. The plurality of first scan drivers and the plurality of second scan drivers perform cascaded transmission according to the clock signal. The disclosure performs cascaded transmission by interposing a clock signal, which can reduce the amount of input signals and simplify the array process.

Growing community of inventors

Hubei, China

Guanghui Hong