Oracle International Corporation

International Business Machines Corporation

Guanghua Shu

Frankie Liu

Suwen Yang

Mark Semmelmeyer

Anatoly Yakovlev

Eric Y Chang

Navaneeth P Jamadagni

Ji Eun Jang

Vincent Lee

Ziad Saleh Shehadeh

John Francis Bulzacchelli

Jonathan E Proesel

Mounir Meghelli

Timothy O Dickson

An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.

Method for training multichannel data receiver timing

We disclose a system, which performs a duty-cycle correction operation for an injection-locked phase-locked loop (PLL). The system first obtains a pattern of positive and negative error pulses at rising and falling edges of a reference clock signal for the injection-locked PLL, wherein the pattern specifies deviations of the reference clock signal from a 50% duty cycle. The system multiplies the pattern of positive and negative error pulses by a duty-cycle distortion (DCD) template, which specifies a sign of a duty-cycle error for the reference clock signal, to calculate duty-cycle distortion values. The system then accumulates the duty-cycle distortion values to produce a duty-cycle-error amplitude. Next, the system multiplies the duty-cycle-error amplitude by the DCD template to produce a duty-cycle correction signal. Finally, the system uses the duty-cycle correction signal to compensate for timing errors in the injection-locked PLL, which are caused by duty-cycle variations in the reference clock signal.

Digitally assisted feedback loop for duty-cycle correction in an injection-locked PLL

The disclosed embodiments relate to a system that controls a phase-locked loop (PLL), eliminating harmonic locking issues during subsampling operation and achieving better noise performance. During operation, the system performs a procedure to measure a first duty cycle that indicates a relationship between a reference signal, which has a frequency F, and a voltage-controlled oscillator (VCO) output signal, which has a frequency Fand is generated by a VCO. The system also performs the procedure to measure a second duty cycle that indicates a relationship between a second reference signal (with a frequency of c*F) and the VCO-output signal. Next, the system determines a frequency and phase relationship between the reference signal and the VCO-output signal based on the first and second duty cycles. Finally, the system uses the frequency and phase relationship to adjust the VCO so that the VCO-output signal, which is used as an output of the PLL, is frequency and phase aligned with the reference signal.

Subsampling phase frequency detector for a divider-less phase-locked loop

During operation, the system uses a differential ring oscillator to generate the output clock signal. Next, the system uses a phase detector to detect errors comprising deviations between edges of the output clock signal and a reference clock signal. The system subsequently uses a frequency-tracking path to adjust a frequency of the differential ring oscillator based on the detected errors, wherein adjusting the frequency involves adjusting a supply voltage for the differential ring oscillator. The system also uses a phase-tracking path to adjust a phase of the differential ring oscillator based on the detected errors, wherein adjusting the phase involves selectively activating an injection pulse generator to inject pulses into the differential ring oscillator. Finally, the system uses a gating mechanism to periodically suppress the injected pulses produced by the injection pulse generator to enable the frequency-tracking path to detect and remediate frequency errors without interference from phase adjustments.

Injection-locking PLL with frequency drift tracking and duty-cycle distortion cancellation

A method and system of equalizing in a decision feedback equalizer is provided. A plurality of adder circuits receives a digital code representing a previously decided symbol from an output of a prior path of a plurality of paths. A decision-making slicer circuit receives an input voltage and a first clock signal. The plurality of adder circuits receives a second clock signal and injects an offset current proportional to the digital code representing the previously decided symbol into a current injection input of the decision-making slicer circuit, at a first edge of the second clock signal. There is a predetermined skew between the first clock and the second clock to control a timing between the injection of the offset current of the plurality of adder circuits and the initiation of a decision-making phase of the decision-making slicer circuit.

High speed DFEs with direct feedback

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San Carlos, CA, United States of America

Guanghua Shu