United Microelectronics Corp.

Guang-Yaw Hwang

Jiunn-Hsiung Liao

Shin-Chi Chen

Chien-Ting Lin

Po-Jui Liao

Shao-Hua Hsu

Tsung-Lung Tsai

Hung-Ling Shih

Chun-Hsien Lin

Chan-Lon Yang

Chia-Wen Liang

I-Chang Wang

Shin-Chuan Huang

Yeng-Peng Wang

Chin-Cheng Chien

Chieh-Te Chen

Yu-Tsung Lai

Che-Hua Hsu

Zhi-Cheng Lee

Yi-Wen Chen

Chiu-Hsien Yeh

Cheng-Guo Chen

Ling-Chun Chou

Jie-Ning Yang

Jung-Tsung Tseng

Pau-Chung Lin

Teng-Chun Tsai

Yi-Wei Chen

Yu-Hsiang Hung

Chun-Yuan Wu

Chia-Lin Hsu

Hsin-Fu Huang

Wen-Han Hung

Chien-Ming Lai

Pei-Yu Chou

Yu-Ru Yang

Min-Chuan Tsai

Po-Cheng Huang

Tong-Jyun Huang

Ying-Tsung Chen

Hsiang-Ying Wang

Tzung-Ying Lee

Cheng-Yu Ma

A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An Oambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.

Oxygen treatment of replacement work-function metals in CMOS transistor gates

A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.

Strained silicon structure

A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.

Semiconductor device having metal gate and manufacturing method thereof

A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer in the first gate trench and the second gate trench, a second work function metal layer respectively formed in the first gate trench and the second gate trench, and a filling metal layer formed on the second work function metal layer. An opening width of the second gate trench is larger than an opening width of the first gate trench. An upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer in the first gate trench.

The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.

Method of manufacturing semiconductor device having metal gates

A pattern forming method is disclosed. The method includes the steps of: forming a dielectric layer on a substrate; forming a first patterned mask on the dielectric layer, wherein the first patterned mask comprises an opening; forming a material layer on the dielectric layer and covering the first patterned mask; forming a second patterned mask on the material layer, wherein the second patterned mask comprises a first aperture; forming a second aperture in the second patterned mask after forming the first aperture, wherein the second aperture and the first aperture comprise a gap therebetween and overlap the opening; and utilizing the second patterned mask as an etching mask for partially removing the material layer and the dielectric layer through the first aperture and the second aperture.

Pattern forming method

A semiconductor device comprising a silicon substrate, a gate structure and a heteroatom-containing epitaxial structure is provided. The gate structure is disposed on a surface of the silicon substrate. The heteroatom-containing epitaxial structure is disposed adjacent to the gate structure and has a major portion and an extension portion, wherein the major portion virtual vertically extends downwards into the silicon substrate from the surface; and the extension portion further extends downwards into the silicon substrate with a tapered cross-section continuing with the major portion.

Method for fabricating semiconductor device

A semiconductor device includes a semiconductor substrate, a gate dielectric layer formed on the semiconductor substrate, and at least a first conductive-type metal gate formed on the gate dielectric layer. The first conductive-type metal gate includes a filling metal layer and a U-type metal layer formed between the filling metal layer and the gate dielectric layer. A topmost portion of the U-type metal layer is lower than the filling metal layer.

A dual damascene process is disclosed. The process includes the steps of: forming a dielectric layer on a substrate; forming a first patterned mask on the dielectric layer, wherein the first patterned mask comprises an opening; forming a material layer on the dielectric layer and covering the first patterned mask; forming a second patterned mask on the dielectric layer, wherein the second patterned mask comprises a first aperture; forming a second aperture in the second patterned mask, wherein the second aperture and the first aperture comprise a gap therebetween; and utilizing the second patterned mask as etching mask for partially removing the material layer and the dielectric layer through the first aperture and the second aperture.

Dual damascene process

Growing community of inventors

Tainan, Taiwan

Guang-Yaw Hwang