Chartered Semiconductor Manufacturing Ltd (Corporation)

Guang Ping Hua

Jun Song

Jun Cai

Keng Foo Lo

Keng-Foo Lo

Igor V Peidous

Vladislav Y Vassiliev

Chock Hing Gan

A transistor structure is manufactured for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

Method of manufacturing ESD protection structure

A transistor structure is provided for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

ESD protection structure

Described is a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology. The UMOS gate is located in a p-substrate and is surrounded by an n-well on either side. Adjacent to one side of the UMOS gate, a first n&plus; diffusion is formed which straddles the first n-well. The n&plus; diffusion together with a p&plus; pickup diffused next to it form the cathode of the SCR (thyristor). Adjacent to the other side of the UMOS gate, a second n&plus; and p&plus; diffusion are formed in a second n-well. The second n&plus; and p&plus; diffusion together with the UMOS gate form the anode of the SCR and the input terminal of the circuit to be protected. The SCR is formed by the first n&plus; diffusion/n-well (cathode), the p-substrate, the second n-well and the second p&plus;/n&plus; diffusion (anode). A latchup immune circuit is achieved by creating a U-shaped gate structure which is lined with a thick gate oxide&mdash;similar to a field oxide&mdash;under the poly gate.

Umos-like gate-controlled thyristor structure for ESD protection

Described is a method of creating a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology. The UMOS gate is located in a p-substrate and is surrounded by an n-well on either side. Adjacent to one side of the UMOS gate, a first n&plus; diffusion is formed which straddles the first n-well. The n&plus; diffusion together with a p&plus; pickup diffused next to it form the cathode of the SCR (thyristor). Adjacent to the other side of the UMOS gate, a second n&plus; and p&plus; diffusion are formed in a second n-well. The second n&plus; and p&plus; diffusion together with the UMOS gate form the anode of the SCR and the input terminal of the circuit to be protected. The SCR is formed by the first n&plus; diffusion/n-well (cathode), the p-substrate, the second n-well and the second p&plus;/n&plus; diffusion (anode). A latchup immune circuit is achieved by creating a U-shaped gate structure which is lined with a thick gate oxide&mdash;similar to a field oxide&mdash;under the poly gate.

UMOS-like gate-controlled thyristor structure for ESD protection

A method to form shallow trench isolation structures with improved isolation fill and surface planarity is described. A pad oxide layer is provided over the surface of a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A thin oxide layer is deposited overlying the silicon nitride layer. An isolation trench is etched through the thin oxide layer, the nitride layer, and the pad oxide layer and into the substrate. The silicon nitride layer exposed within the trench is etched to form a lateral undercut leaving a projection of the thin oxide layer and exposing a portion of the underlying pad oxide layer. The thin oxide layer and the exposed portion of the pad oxide layer are etched away thereby exposing portions of the surface of the substrate. A liner oxide is grown on the exposed portions of the semiconductor substrate within the isolation trench and on the surface of the substrate. A layer of isolation dielectric is deposited overlying the liner oxide and the silicon nitride and filling the isolation trench. The isolation dielectric is polished away stopping at the silicon nitride layer. The remaining silicon nitride etched away. The isolation dielectric and the pad oxide are etched away from the surface of the semiconductor substrate. The fabrication of the integrated circuit device is completed.

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