Taiwan Semiconductor Manufacturing Comp. Ltd.

Guang-Cheng Wang

Kuo-Ji Chen

Yu-Ren Chen

Ming-Hsin Yu

Shiu-Ko JangJian

Ying-Lang Wang

Alan S Roth

Ta-Pen Guo

Eric Soenen

Wen-Shen Chou

Chyi-Tsong Ni

Bo-Ting Chen

Shih-Chi Lin

Szu-An Wu

Ker-Min Chen

Chia-Hui Chen

Justin Shi

Ying-Chih Hsu

Wen-Long Lee

Shang-Hsuan Chiu

Jun Wu

Yueh Chiang

Dong-Xuan Lu

Yi-An Jian

Ming-Xiang Liu

A flip-flop includes a first set of transistors of a first type being located in a first row and a second set of transistors of a second type being located in a second row. The second type being different from the first type. The first and second set of transistors include a first master latch circuit and a second master latch circuit. The first and second master latch circuit are separated from each other in the first direction by a first distance. A first output signal of the first and second master latch circuit is a first input signal of the first master latch circuit and the second master latch circuit. A second output signal of the first and second master latch circuit is a second input signal of the first and second master latch circuit.

Integrated circuit and method of forming the same

One or more systems and techniques for communicating a signal between a first chip and a second chip using one or more circuits are provided. If the signal corresponds to a first voltage, one or more voltages are provided to one or more locations and a capacitive load is charged using a pull-up driver that is connected to a power supply. If the signal corresponds to a second voltage, one or more voltages are provided to one or more locations and the capacitive load is discharged using a pull-down driver that is connected to ground. When the first chip is powered off, a fail-safe mode is provided by configuring a cross control circuit to generate a bias to control one or more transistors.

Controlling voltage at pad

A multiple device voltage electrostatic discharge (ESD) clamp includes a trigger circuit, first and second inverters, and an ESD discharge path. The trigger circuit includes a resistor having a first terminal electrically connected to a first voltage supply node, and a capacitor having a first terminal electrically connected to a second voltage supply node. The first inverter has an input terminal electrically connected to second terminals of the resistor and the capacitor. The second inverter has a power terminal electrically connected to an output terminal of the first inverter. The ESD discharge path has a first end electrically connected to the first voltage supply node, and a second end electrically connected to a third voltage supply node, and includes a first transistor controlled by the first inverter, and a second transistor controlled by the second inverter.

Multiple device voltage electrostatic discharge clamp

A threshold voltage detection apparatus comprises a voltage level up-shifter and a voltage level down-shifter. The threshold voltage detection apparatus is placed at a circuit fabricated in a low voltage semiconductor process. The threshold voltage detection apparatus receives an input signal having a wide range and generates output signals comprising the logic of the input signal, but having a voltage range suitable for the low voltage circuit. The threshold voltage detection apparatus ensures that the low voltage circuit operates in a range to which the low voltage semiconductor process is specified.

Threshold voltage detection apparatus

A voltage tolerant input/output circuit coupled to an input/output pad, and is able to support a voltage overdrive operation of approximately twice an operational voltage, and have an input tolerance of approximately three times the operational voltage. The circuit includes a pull-up driver, a P-shield, an N-shield, a pull-down driver and a cross-control circuit. The pull-up driver is coupled to a power supply. The P-shield has an N-well and is coupled to the pull-up driver at a node C, and coupled to the input/output pad. An N-shield is also coupled to the input/output pad. A pull-down driver is coupled between ground and the N-shield at a node A. A cross-control circuit is configured to detect voltages at: the node A, the node C, and the input/output pad. The cross-control circuit is configured to output control signals to the P-shield and the N-shield based on the detected voltages.

3X input voltage tolerant device and circuit

An amplifier drives the gate of a master source follower and of at least one slave source follower to form a low-dropout (LDO) regulator. Alternatively, a charge pump drives the master source follower to form the regulator. Additional slave source followers may be used in conjunction with the charge pump and the master source follower to improve the regulator performance.

LDO regulators for integrated applications

In a first pair of stacked PMOS devices comprising a first PMOS device and a second PMOS device, a first pumping circuit is coupled between a gate of the first PMOS device and a P pre-driver signal. In a second pair of stacked NMOS devices comprising a first NMOS device and a second NMOS device, a second pumping circuit is coupled between a gate of the first NMOS device and an N pre-driver signal. The pumping circuits recognizing the transition from the pre-driver signals provide a voltage to the gate of the first PMOS device and of the first NMOS device so that the first PMOS and NMOS devices are turned on better. As a result, their voltage Vds peaks are suppressed to a safe level; the devices avoid hot-carrier degradations; and their lifetimes are prolonged.

Over-drive circuit having stacked transistors

An electrostatic discharge (ESD) clamp includes a first power source configured to provide a first power supply voltage, a power supply node coupled to the first power source and receiving the power supply voltage; and a first NMOS transistor and a second NMOS transistor coupled in series and between the power supply node and a VSS node. The first NMOS transistor and the second NMOS transistor are low nominal VDD devices with maximum endurable voltages lower than the power supply voltage. The ESD claim further includes an ESD detection circuit including a capacitor coupled between the power supply node and a gate of the second NMOS transistor, and a resistor coupled between the gate of the second NMOS transistor and the VSS node.

ESD clamp for high voltage operation

A circuit, includes first, second, and third inverters. The first inverter has a first input coupled to a first port and a first output coupled to a second port. The second inverter has a second input coupled to the second port and a second output coupled to the first port. The third inverter has a third input coupled to the first port through a first capacitor and to a third port. The third inverter has an output coupled to the second port through a second capacitor. The circuit receives a signal having a voltage between a first voltage potential and a second voltage potential and in response outputs a signal having a voltage between the second voltage potential and a third voltage potential. The third voltage potential is higher than the first and second voltage potentials with respect to ground.

Voltage level shifter

A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a switching device coupled between a drain of one of the pair of PMOS transistors and a drain of the NMOS transistor, wherein the pair of PMOS transistors are high voltage transistors and the switching device is off when the VCCL is below a predetermined voltage level, and the switching device is on when the VCCL is above the predetermined voltage level.

Low leakage voltage level shifting circuit

A method for spin-on wafer cleaning. The method comprises controlling spin speed and vertical water jet pressure. The vertical jet pressure and the spin speed are substantially maintained in inverse proportion. Wafer spin speed is between 50 to 1200 rpm. Vertical wafer jet pressure is between 0.05 to 100 KPa.

Growing community of inventors

Zhubei, Taiwan

Guang-Cheng Wang