Micron Technology Incorporated

Nio Usa, Inc.

Black Sesame Technologies Inc.

Microsoft Technology Licensing, LLC

Black Sesame International Holding Limited

Intel Corporation

Linkedin Corporation

Guan Wang

Ali Feiz Zarrin Ghalam

Qiang Tang

Luigi Pilolli

Anthony Tao Liang

Yu Cheng Chen

Prashant Jain

Shaobo Liu

Christian Sutherland-Wong

Ximeng Zhang

Vidya Elangovan

Yuchen Zhao

Mike Derezin

Chin-Yu Chen

Jongin Kim

Jeff Lee

Fei Xiao

Agatino Massimo Maccarrone

Huan Hoang

Christopher Francis Pouliot

Mengting Tsai

Hao Du

A memory sub-system including a memory device, wherein the memory device includes a circuit, operatively coupled to an array data bus of a memory array, and control logic, operatively coupled with the circuit, to perform operations including: deserializing a serial data stream in a first time domain to generate at least one of a set of rising data portions or a set of falling data portions; and synchronizing the at least one of the set of rising data portions or the set of falling data portions in a second time domain using at least one of a set of rising edge clock signals or a set of falling edge clock signals generated by a ring counter portion.

Memory device deserializer circuit with a reduced form factor

An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.

Data bus duty cycle distortion compensation

A memory device includes a plurality of input/output (I/O) nodes, a circuit, a latch, a memory, and control logic. The plurality of I/O nodes receive a predefined data pattern. The circuit adjusts a delay for each I/O node as the predefined data pattern is received. The latch latches the data received on each I/O node. The memory stores the latched data. The control logic compares the stored latched data to an expected data pattern and sets the delay for each I/O node based on the comparison.

Write training in memory devices by adjusting delays based on data patterns

A method of instance segmentation, comprising, defining a bounding box, depth mapping the bounding box, sorting the depth map, estimating stability due to noise of the sorted depth map, detecting low frequency jumps of the sorted depth map based on the estimated stability, detecting high frequency jumps of the sorted depth map, comparing the detected low frequency jumps and the detected high frequency jumps, detecting at least one of a largest object and a closest object based on the comparison and pixel masking the at least one of the largest object and the closest object.

Fast instance segmentation

A memory device including a memory array operatively coupled to an array data bus and a deserializer circuit operatively coupled with the array data bus. The deserializer circuit includes a first ring counter including a first set of flip-flops to sequentially output a set of rising edge clock signals based on a reference clock input and a second ring counter portion including a second set of flip-flop circuits to sequentially output a set of falling edge clock signals based on the reference clock input. A rising data circuit portion of the deserializer circuit includes a set of flip-flops that each receive a rising data portion from a respective latch circuit in response to a rising edge clock signal. A falling data circuit portion of the deserializer circuit includes a set of flip-flops that each receive a falling data portion from a respective latch circuit in response to a falling edge clock signal. The third set of flip-flops outputs the set of rising data portions and the fourth set of flip-flop circuits outputs the set of falling data portions to generate a synchronized data stream to output to the array data bus in response to a common clock signal.

A method of mapping and localization is disclosed that includes, reconstructing a point cloud and a camera pose based on VSLAM, synchronizing the camera pose and a GPS timestamp at a first set of GPS coordinate points and transforming the first set of GPS coordinate points corresponding to the GPS timestamp into a first set of ECEF coordinate points. The method also includes determining a translation and a rotation between the camera pose and the first set of ECEF coordinate points, transforming the point cloud and the camera pose into a second set of ECEF coordinates based on the translation and the rotation and transforming the point cloud and the camera pose into a second set of GPS coordinate points. The method further includes constructing and storing a key-frame image, a key-frame timestamp and a key-frame GPS based on the second set of GPS coordinate points.

3D point cloud map alignment with open street map for outdoor 6D localization on mobile platforms

A method of camera localization, comprising, receiving a camera image, receiving a LiDAR point cloud, estimating an initial camera pose for the camera image, sampling an initial set of depth projections within the LiDAR point cloud, measuring a similarity of the initial camera pose to the initial set of depth projections and deriving a subsequent set of depth projections based on the measured similarity.

Monocular camera localization in large scale indoor sparse LiDAR point cloud

Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

Internal clock distortion calibration using DC component offset of clock signal

An input/output (I/O) circuit provides a direct current (DC) bias between I/O stages to control duty cycle of the I/O. The I/O circuit can include one or more predriver stages and one or more output stages. The predriver stages can collectively be referred to as a predriver stage, and the output stages can collectively be referred to an output stage. The output stage for a transmitter drives the signal line. The output stage for an input buffer provides a receive signal for processing by the receiver. The I/O circuit includes a control circuit to control the DC bias between the stages to provide trim adjustment of a duty cycle for the output stage.

Duty cycle control circuitry for input/output (I/O) margin control

Write training in memory devices

Embodiments of the present disclosure are directed to providing an Augmented Reality (AR) navigation display in a vehicle. More specifically, embodiments are directed to rendering AR indications of a navigation route over a camera video stream in perspective. According to one embodiment, visual tracking can be performed on features in the video data and camera pose, i.e., a matrix encapsulating position and orientation, can be determined for each frame of video based on both the visual tracking and navigation sensor data. These separately determined camera poses can then be merged or fused into a single camera pose that is more accurate and more stable and which can then be used in rendering more realistic AR route indicators onto the video of the real-world route captured by the camera.

Sensor fusion methods for augmented reality navigation

Embodiments of the present disclosure are directed to an augmented reality based user's manual for a vehicle implemented as an application on a mobile device which allows the user to point a mobile phone, tablet or an augmented reality headset at any part of the vehicle interior or exterior and experience augmented annotations, overlays, popups, etc. displayed on images of real parts of the car captured by the user's mobile device. Embodiments provide for estimating the camera pose in six degrees of freedom based on the content of the captured image or video and using a neural network trained on a dense sampling of a three-dimensional model of the car rendered with realistic textures to identify and properly align the augmented reality presentation with the image of the vehicle being captured by the mobile device.

Growing community of inventors

San Jose, CA, United States of America

Guan Wang