Samsung Electronics Co., Ltd.

Gu-Sung Kim

Kang-Wook Lee

Dong-Hyeon Jang

Keum-Hee Ma

Seung-Duk Baek

Sa-Yoon Kang

Young-Hee Song

Yong-Chai Kwon

Se-Yong Oh

Jae-Sik Chung

Suk-Chae Kang

Seong-Il Han

Min-Young Son

Donghan Kim

Dong-Ho Lee

Jong-woo Kim

Se-Young Jeong

Jin-Hyuk Lee

Seung-Kon Mok

Si-Hoon Lee

Yun-hyeok Im

Seung-Ho Ahn

Sun-Wook Heo

Jung-Hang Yi

A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

Chipstack package and manufacturing method thereof

A system-in-package, comprising a wafer level stack structure, including at least one first device chip including a first device region having a plurality of input/output(I/O) pads, and at least one second device chip including a second device region having a plurality of input/output(I/O) pads and a second peripheral region surrounding the second device region, wherein the size of the second device region is different from the size of the first device region, wherein the at least one first device chip and the at least one second device chip have approximately equal size; and a common circuit board to which the wafer level stack structure is connected.

Wafer level stack structure for system-in-package and method thereof

A method of forming a wafer level stack structure, including forming a first wafer including a first device chip, wherein the first device chip includes a plurality of input/output (I/O) pads, forming a second wafer including a second device chip, wherein each second device chip contains a second plurality of I/O pads, the second device chip is approximately equal in size to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A method of forming a system-in-package for containing a wafer level stack structure, including forming a wafer level stack structure including a first device chip having a first plurality of input/output (I/O) pads and a second device chip having a second plurality of I/O pads, and forming a common circuit board to which the wafer level stack structure is connected.

A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected.

A structure for improving electrical performance and interconnection reliability of an integrated circuit in a Wafer Level Packaging (WLP) application comprises an air pad located under an interconnection metal solder pad. Using a low dielectric material such as air underlying the interconnection pad, pad capacitance is reduce, thereby improving the speed of associated electrical signal transitions. By configuring the structure to have interconnection pad supports at only a limited number of pad periphery points, a cured soldered connection can absorb mechanical stresses associated with divergent movement between a connecting wire and the interconnection pad. Such a structure can be manufactured using the steps of: 1) depositing a soluble base material in a cavity on an IC substrate, 2) depositing a metal pad layer on the soluble base layer, and 3) dissolving the soluble base layer, leaving an air gap under the metal pad layer which is supported by the periphery supports.

Method for manufacture of wafer level package with air pads

A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only 'known-good die' before the next layer of chips is attached thereby increasing the production rate and improving the yield.

Chip stack package and manufacturing method thereof

An image sensor device including a protective plate may be manufactured from an image sensor chip having an active surface and a back surface opposite to the active surface. The image sensor chip may include chip pads formed in a peripheral region of the active surface, a microlens formed in a central region of the active surface and an intermediate region between the peripheral and central regions. A protective plate may be attached to the intermediate region of the active surface of the image sensor chip using an adhesive pattern that is sized and configured to maintain a separation distance between the protective plate and the microlens formed on the image sensor chip. Conductive plugs, formed before, during or after the manufacture of the image sensor chip circuitry may provide electrical connection between the chip pads and external connectors.

Image sensor device and method of manufacturing the same

A multi-chip package (MCP) is provided. The MCP comprises a plurality of stacked semiconductor chips, each including a chip pad and a first insulating layer overlying the chip pad with an opening to expose a portion of the chip pad. Each chip additionally includes a pad redistribution line formed on the first insulating layer and a second insulating layer covering the pad redistribution line. A via hole is formed through the chip, the first insulating layer, a pad redistribution line and the second insulating layer. The MCP further includes a protective layer formed on the bottom of the lowest semiconductor chip. The protective layer includes a conductive pad formed opposite the bottom of the lowest semiconductor chip. A conductive bar extends through the via holes of the stacked semiconductor chips, from the conductive pad, and is electrically connected to the pad redistribution line of the stacked semiconductor chips.

Multi-chip package (MCP) with a conductive bar and method for manufacturing the same

An assembly may include a wafer and a plate may be mounted on the wafer. The wafer may have image sensor chips and scribe lines demarcating each image sensor chip. The image sensor chip may include an active surface. Chip pads and a micro-lens may be provided on the active surface. A photo-sensitive adhesive pattern may be provided between the plate and a region of the active surface between the chip pads and the micro-lens. An image sensor device implementing an image sensor chip having an individual plate may also be provided.

Assembly having wafer with image sensor chips, a photo-sensitive adhesive pattern and plate thereof and method of manufacturing the same

A semiconductor package includes a semiconductor chip, a circuit board at which a wire pattern is formed, and a metal structure including a portion inserted through an opening of the circuit board and upon which the semiconductor chip rests. With the semiconductor chip in direct contact with the metal structure, thermal characteristics improve. With the circuit board supported by the metal structure, mechanical stability improves.

Semiconductor package

An image sensor device and methods thereof. In an example method, a protective layer may be formed over at least one microlens. An adhesive layer may be formed over the protective layer. The adhesive layer may be removed so as to expose the protective layer. The protective layer may be removed so as to expose the at least one microlens, the exposed at least one microlens not including residue from the adhesive layer. The at least one microlens may have an improved functionality due at least in part to the lack of residue from the adhesive layer. In an example, the at least one microlens may be included in an image sensor module.

Image sensor device and methods thereof

A solder bump structure may be formed using a dual exposure technique of a photoresist, which may be a positive photoresist. The positive photoresist may be coated on an IC chip. First openings may be formed at first exposed regions of the photoresist by a first exposure process. Metal projections may be formed in the first openings. A second opening may be formed at a second exposed region of the photoresist by a second exposure process. The second exposed region may include non-exposed regions defined by the first exposure process. A solder material may fill the second opening and may be reflowed to form a solder bump. The metal projections may be embedded within the solder bump.

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Seongnam-si, South Korea

Gu-Sung Kim