Samsung Electronics Co., Ltd.

Epworks Co., Ltd.

Gu S Kim

Young Sun Kim

Dong Hyeon Jang

Seung H Ahn

Yong Hwan Kwon

Jae Man Park

Sa Yoon Kang

Jong Guk Kim

Seung Kon Mok

Seung Duk Baek

Jae Myung Park

Sang Eon Oh

Kang Wook Lee

Min Kyo Cho

Kun Kul Ryoo

Jae Sik Chung

Jae June Kim

A method for regenerating silicon from silicon waste includes: placing and mixing silicon waste, a solvent having pH of approximately 5 to approximately 6, and a surfactant within a container; and injecting air into the container to separate floating matters and precipitates. Accordingly, since silicon is easily separated from the silicon waste, the regeneration yield of silicon is increased. Since the regenerated silicon is recyclable, it may be possible to obtain important substitution effect of high-purity silicon the entire amount of which depends on import. Moreover, environmental pollution may be reduced because the amount of the silicon waste disposed of by burial is decreased.

Method for regenerating silicon from silicon waste and silicon manufactured using the same

An electronic module comprises a monolithic microelectronic substrate including at least one integrated circuit die, e.g., a plurality of unseparated memory dice or a mixture of different types of integrated circuit dice. The monolithic substrate further includes a redistribution structure disposed on the at least one integrated circuit die and providing a connector contact coupled to the at least one integrated circuit die. For example, the connector contact may be configured as edge connector contact for the module. The redistribution structure may be configured to provide a passive electronic device, e.g., an inductor, capacitor and/or resistor, electrically coupled to the at least one integrated circuit die and/or the redistribution structure may comprise at least one conductive layer configured to provide electrical connection to a contact pad of an electronic device mounted on the substrate. Methods of fabricating electronic modules are also discussed.

Wafer-level electronic modules with integral connector contacts

A wafer level chip package has a redistrubution substrate, at least one lower semiconductor chip stacked on the redisctribution substrate, and an uppermost semiconductor chip. The redistribution substrate has a redistribution layer and substrate pads connected to the redistribution layer. The lower semiconductor chip is stacked on the redistribution layer and may have through holes for partially exposing the redistribution layer, the through holes corresponding to the substrate pads, and having conductive filling material filling the through holes. The uppermost semiconductor chip may have the same elements as the lower semiconductor chip, and may be flip chip bonded to the through holes. The package may further have a filling layer for filling areas between chips, a metal lid for coating most of the external surfaces, and external connection terminals formed on and electrically connected to the exposed redistribution layer from the first dielectric layer of the redistribution substrate.

Wafer level stack chip package and method for manufacturing same

An apparatus for burn-in test comprising, a socket body including an accommodation groove in which an integrated circuit chip is accommodated to be tested, a step sill portion formed around the accommodation groove, a plurality of inner leads formed on the step sill portion, a plurality of outer leads protruded from the socket body and electrically connected to said inner leads through the socket body, and a supporting element attached to opposite inside walls of the accommodation groove to support the integrated circuit chip, and a method for burn-in test comprising the steps of: (a) mounting an integrated circuit chip to be tested in the accommodation groove; (b) bonding pads of the integrated circuit chip with the corresponding inner leads through a plurality of wires; (c) mounting the socket body on a test board by the outer leads and applying test pattern signals to the integrated circuit chip through the inner and outer leads in the condition of high temperature and high voltage; and (d) severing and removing the wires.

Method for performing a burn-in test

Disclosed herein is a high thermal emissive semiconductor device package which comprises a substrate having a plurality of external connection leads, a plurality of connection lands and wires between the leads and the lands; at least one semiconductor chips mounted on the substrate; bonding wires electrically connecting bonding pads of the chip and the connection lands of the substrate; a heat spreader with high thermal conductivity, which is attached to the upper surface of the bonding pads of the chip by insulating adhesives with good thermal conductivity; and a metal cap which is in contact with the upper surface of the heat spreader via thermal compounds and encapsulates the whole components by being sealed to the substrate. The high thermal emissive semiconductor device packages have advantageous that they efficiently emit heat generated during the operation of components and that they may be applied to various semiconductor devices which can be produced at low costs.

High thermal emissive semiconductor device package

A process for manufacturing a thin profile semiconductor package by means of TAB (tape automated bonding). A barrier metal layer is formed on bonding pads formed on portions of a chip covered with insulating layers. A photoresist layer is formed on the resultant structure, and patterned so as to expose the barrier metal layer, and then bumps are formed on the barrier metal layer as high as the photoresist layer. The semiconductor package is completed by bonding the bumps and inner lead portions of the TAB tape. The photoresist remains on the completed package as a permanent protective layer.

Method for making a thin profile semiconductor package

A semiconductor memory module is formed of semiconductor packages respectively having at least one defect data line combined to be mounted to a module substrate which has two rows of auxiliary pads for excluding the defect data line of the mounted semiconductor packages from overall data lines of the module to thus attain more than a required memory capacity. By connecting the auxiliary pads with coupling units of resistors or jumper cables to isolate the defect data lines, the semiconductor memory module achieves the required memory capacity and utilizes defective semiconductor packages to reduce manufacturing costs, to attain excellent compatibility resulting from employing all kinds of semiconductor packages, and to simplify the data line connection process. Further, reworking semiconductor package is easy which improves yield, and humid air is prevented from permeating into the interior of the molding resin thereby preventing failures such as disconnection of wires and improving reliability.

Semiconductor memory module

A method of manufacturing and a structure of a semiconductor device has an I/O terminal whereby when individual semiconductor chips are separated from the semiconductor wafer manufactured according to this invention, the terminals are exposed on the edges of the semiconductor chip allowing for the interconnection of the terminals when the semiconductor chips are stacked. The bump electrode is formed using metal masks and magnets by mounting a solder ball on an aperture of a first mask to form the solder bump on an electrode pad provided on a semiconductor wafer. A conductive material forms a conductive pattern between the solder bumps of the individual semiconductor chips using an aperture of a second mask. The individual semiconductor chips which are separated from the semiconductor wafer are then easily stacked and packaged by use of the I/O terminals on the sides of the individual semiconductor chips.

Manufacturing method of a semiconductor device

The present invention relates to a semiconductor package which is loaded with a plurality of high-performance integrated circuits for high-performance systems such as super computers and large-sized computers. According to the invention, the packaging density of the semiconductor is doubled by stacking upper and lower members and forming substrates loaded with a plurality of chips in a multistep structure so that the size of computers can be minimized and heat emission efficiency can be improved by forming heat sinks in a fin-pin shape.

Method of manufacturing semiconductor package

A semiconductor chip bonding process is disclosed, and the process comprises the steps of forming a first Au ball using a wire ball bump bonding apparatus, stacking a second Au ball on the first Au ball, stacking a Pb ball on the second Au ball using the wire ball bump bonding apparatus, and bonding the chip to a substrate, wherein the conventional complicated BUMP manufacturing process is omitted due to the CHIP BONDING technique during the assembling process, so that the formation process is shortened and the defect rate during the chip bonding is minimized, thereby the manufacturing cost can be saved.

Growing community of inventors

Seoul, South Korea

Gu S Kim