Infineon Technologies Ag

Grit Schwalbe

Klaus Goller

Elard Stein Von Kamienski

Kae-Horng Wang

Klaus Feldner

Alexander Reb

Thomas Ruder

In a method of contacting terminals, a substrate having a first terminal and a second terminal is provided, a terminal surface of the first terminal being located at a shorter distance from a substrate surface than a surface of the second terminal. A first insulating layer, in which a contact via is formed for exposing the terminal surface of the first terminal, is formed on the substrate surface. The contact via is filled with a conductive material, and a second insulating layer is formed on the first insulating layer and on the contact via filled with the conductive material. Using an etching mask, a first recess for exposing the conductive material filling the contact via, and a second recess are etched through the second and first insulating layers for exposing the second terminal surface. A conductive material for producing first and second contact terminals is introduced into the first and second recesses. This is to achieve that the second terminal is contacted in the production of the second contact terminal.

Method and arrangement for contacting terminals

The invention relates to a process for patterning dielectric layers. A photoresist layer is applied to the dielectric layer and patterned. Then, the pattern which has been predetermined by the resist mask is transferred to the dielectric layer. The incineration of the resist mask is carried out a temperature of 50&#xb0; C. to 200&#xb0; C., with the oxygen plasma being generated from a gas which has an oxygen content of 40 to 60% by volume. During a subsequent step of cleaning the patterned dielectric layer using dilute hydrofluoric acid, the trenches which have been introduced into the dielectric layer are widened to a significantly lesser extent than after incineration under the conditions which have previously been customary.

Method for patterning dielectric layers on semiconductor substrates

A method for providing bitline contacts in a memory cell array includes a plurality of bitlines disposed in a first direction, the bitlines being covered by an isolating layer, a plurality of wordlines disposed in a second direction perpendicular to the first direction above the bitlines, and memory cells disposed at the points at which the bitlines and wordlines cross each other. According to a first aspect of the present invention, the isolating layer is removed from the bitlines at the portions that are not covered by the wordlines, whereas the areas between the bitlines remain unaffected. Alternatively, the isolating layer is removed from the whole cell array. Then, an electrical conductive material is provided on the exposed portions of the bitlines. The method is used to provide bitline contacts in a nitride read only memory (NROM&#x2122;) chip.

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Dresden, Germany

Grit Schwalbe