International Business Machines Corporation

Globalfoundries Inc.

Samsung Electronics Co., Ltd.

Advanced Micro Devices Corporation

Chartered Semiconductor Manufacturing Ltd (corporation)

Applied Materials, Inc.

Globalfoundries U.S. 2 LLC

Auriga Innovations, Inc

Griselda Bonilla

Andrew Herbert Simon

Ronald G Filippi

Naftali Eliahu Lustig

Samuel S Choi

Junjing Bao

Elbert Emin Huang

Chih-Chao Yang

Kaushik Chanda

Stephan Grunow

Son Van Nguyen

Baozhen Li

Alfred Grill

Xiao Hu Liu

Takeshi Nogami

Ping-Chuan Wang

Satyanarayana Venkata Nitta

Daniel C Edelstein

Christopher J Penny

Deepika Priyadarshini

Qinghuang Lin

Thomas M Shaw

Christos Dimitrios Dimitrakopoulos

Terry Allen Spooner

Shyng-Tsong Chen

Chao-Kun Hu

Lawrence Alfred Clevenger

Shom Ponoth

Thomas W Dyer

Stephen Edward Greco

James A Culp

Matthew S Angyal

Theodorus E Standaert

Wai-Kin Li

Dirk Pfeiffer

Deborah A Neumayer

John Albrecht Ott

David Lee Rath

James Bowler Hannon

Howard Smith Landis

Michael Wayne Lane

Darryl D Restaino

Eric Gerhard Liniger

Kelly Malone

Thomas J Haigh, Jr

Satoshi Oida

Sujatha Sankaran

E Todd Ryan

Robert Dennis Miller

Sampath Purushothaman

Stephen McConnell Gates

Matthew Earl Colburn

Hosadurga K Shobha

Muthumanickam Sankarapandian

Willi Volksen

John Christopher Arnold

Roger Allan Quon

William J Cote

James Patrick Doyle

Dan Moy

Paul Stephen McLaughlin

Satya Venkata Nitta

Geraud J Dubois

Johnny Widodo

Robert Daniel Edwards

Samuel S S Choi

Xio Hu Liu

Jeffrey P Gambino

Takashi Ando

John Ulrich Knickerbocker

Yun Yu Wang

Hemanth Jagannathan

Timothy Harrison Daubenspeck

Daniel Joseph Friedman

Kevin Shawn Petrarca

Jae Hun Kim

Erdem Kaltalioglu

David Brian Stone

Katsuyuki Sakuma

Barry P Linder

David L Questad

Robert Allen Groves

Kaushik Arun Kumar

Yiheng Xu

Shidong Li

Krishna R Tunga

Mark C H Lamorey

Andrew Tae Kim

Ernest Y Wu

Lijuan Zhang

Kai Zhao

Jae-hak Kim

Steven E Molis

James H Stathis

Lei Shan

Ronald Anthony DellaGuardia

Stephen Alan Cohen

Pak Leung

Joshua L Herman

Samuel Sung Shik Choi

A base substrate, high-k substrate layers on the base substrate with discrete decoupling capacitors embedded, high density substrate layers on the high-k substrate layers supporting wiring and wiring spacing of less than 2 up to about 10 micron width, pitch connectivity between the upper surface of the base substrate and a lower surface of the set of high density substrate layers supports less than 50 up to about 300 micron pitch, the pitch connectivity on an upper surface of the set of high density substrate layers supports less than about 150 micron pitch. A method including attaching a set of metal posts at each contact on a lower surface of a set of high density substrate layers, attaching to a handler, attaching an interconnect layer to a base substrate, and attaching the set of high density substrate layers to the base substrate while aligning each metal post with a contact.

Electronic substrate stacking

An integrated circuit package substrate (ICPS) system includes a die including a first array of connectors and a substrate including a second array of connectors that is configured to be thermocompression bonded to the first array of connectors at a bonding temperature that is above a solder melting temperature. The first die is bonded to the substrate such that the first die is asymmetric with respect to a substrate center, and the second array of connectors is adjusted, at an alignment temperature that is below the solder melting temperature, for thermal expansion to the bonding temperature with respect to a reference point that is not a first die center.

Asymmetric die bonding

An interconnect level is provided on a surface of a substrate that has improved crack stop capability. The interconnect level includes at least one wiring region including an electrically conductive structure embedded in an interconnect dielectric material having a dielectric constant of less than 4.0, and a crack stop region laterally surrounding the wiring region. The crack stop region includes a crack stop dielectric material having a dielectric constant greater than the dielectric constant of the interconnect dielectric material. The crack stop region may be devoid of any metallic structure, or it may contain a metallic structure. The metallic structure in the crack stop region, which is embedded in the crack stop dielectric material, may be composed of a same, or different, electrically conductive metal or metal alloy as the electrically conductive structure embedded in the interconnect dielectric material.

Dielectric crack stop for advanced interconnects

A method for constructing an advanced crack stop structure is described. An interconnection structure is formed comprised of a plurality of levels. Each level has an interconnect structure section and a crack stop section. In a first level of the interconnection structure, a high modulus layer is formed in the crack stop recess but not the interconnect recess and a barrier layer and a conductive metal layer is formed in both the interconnection recess and the crack stop recess of the first level. In a second level of the interconnection structure and the crack stop structure, a second high modulus layer is formed in the crack stop recess but not the interconnect recess and a barrier layer and a conductive metal layer is formed in both the interconnection recess and the crack stop recess of the second level. The barrier layers and high modulus layers are deposited in different steps.

Advanced crack stop structure

An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a first plurality of levels. Each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The structure also includes a crack stop area which includes a crack stop structure having a second plurality of levels. The interconnect and crack stop structures have an equal number of levels. A third plurality of the crack stop structure levels include a high modulus layer unique to the respective crack stop structure level as compared to the corresponding interconnect structure level.

An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level.

A method for creating an integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level. In another aspect of the invention, a method for producing the structure is described.

A method is presented for forming a stacked metal-insular-metal (MIM) capacitor with self-aligned contact. The method includes forming a first electrode plate over a first interlayer dielectric (ILD), forming a first spacer adjacent the first electrode plate, forming a first insulating layer over the first electrode plate, forming a second electrode plate over the first insulating layer, and forming a second spacer adjacent the second electrode plate and the first insulating layer. The method further includes forming a second insulating layer over the second electrode plate, forming a third electrode plate over the second insulating layer, forming a third spacer adjacent the third electrode plate and the second insulating layer, and forming a second ILD over the third electrode plate. The method also includes forming a first via through the second ILD and directly contacting the second spacer such to prevent the first via from contacting the second electrode plate.

Stacked MIM capacitors with self-aligned contact to reduce via enclosure

An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a first plurality of levels. Each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The structure also includes a crack stop area which includes a crack stop structure having a second plurality of levels. The interconnect and crack stop structures have an equal number of levels. A third plurality of the crack stop structure levels include a high modulus layer unique to the respective crack stop structure level as compared to the corresponding interconnect structure level. In another aspect of the invention, a method for fabricating the structure is described.

An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level. In another aspect of the invention, a method for producing the structure is described.

Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.

Air gap and air spacer pinch off

Methods of forming an interconnect structure include depositing a first conductive material on a substrate. Aspects include subtractively etching the conductive material to form a patterned first conductive layer, and depositing a dielectric layer on interconnect structure. Aspects also include depositing a second conductive material on the dielectric layer and removing the second conductive material through the top of the second metal liner.

Interconnect structure having subtractive etch feature and damascene feature

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Fishkill, NY, United States of America

Griselda Bonilla