Ati International Srl

Ati Technologies Ulc

Ati Technologies Inc.

Peraso Technologies Inc.

Advanced Micro Devices Corporation

Other

Grigori Temkine

Oleg Drapkin

Osamu Nagashima

Joseph D Macri

Olge Drapkin

Filipp Chekmazov

Gordon Caruk

Bradley Robert Lynch

Arvind Bomdica

Alexander Tomkins

Kevin Yikai Liang

Kristina Au

Craig Farnsworth

Milivoje M Aleksic

Kongning Li

Charles Leung

Kevin O'Neil

Michael Foxcroft

Paul Edelshteyn

Steven Turner

Arash Tabibiazar

Greg Vansickle

Edward George Callway

Aris Balatsos

Antonio A Rinaldi

Mikhail Rodionov

Ming L So

Kuldip Sahdra

Peter L Rosefield

Chak Cheung Ho

Siji Menokki Kandiyil

Marcus Ng

Samu Suryanarayana

Yamin Du

Ngar Sze Chan

Roche Thambimuthu

Mikhall Rodionov

Ho Ming Wan

A method in a wireless communications assembly having an antenna, a transceiver and a baseband processor, includes: at the transceiver: receiving, from the antenna, a modulated carrier signal having a carrier frequency and containing payload data; demodulating the carrier signal to extract a baseband signal having a baseband frequency and containing the payload data; generating from the baseband signal, at a converter, a digital baseband signal containing the payload data; at an encoder: receiving the digital baseband signal from the converter; generating an encoded digital baseband signal encoding the payload data for transmission at an operating frequency; the encoded digital baseband signal having at least a threshold proportion of signal level transitions that, when transmitted at the operating frequency, have transition frequencies outside a predefined restricted frequency band; and transmitting the encoded digital baseband signal to the baseband processor via an interface at the operating frequency.

Method and system for interference mitigation in wireless communications assemblies

Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.

Methods and apparatus for processing graphics data using multiple processing circuits

A wireless receiver automatic gain control system includes: a coarse amplification subsystem that receives and amplifies a carrier-modulated signal; a demodulator that generates a baseband signal from the amplified carrier-modulated signal; a fine amplification subsystem that amplifies the baseband signal; and a controller connected to the amplification subsystems. The controller: obtains a unified gain value for the amplification subsystems; based on the unified gain value, selects (i) one of a plurality of coarse gain values defining a set of coarse gain steps each spanning a plurality of unified gain steps, and (ii) one of a plurality of fine gain values defining a set of fine gain steps each spanning a single unified gain step; and sets (i) the gain of the coarse amplification subsystem to the selected coarse gain value, and (ii) the gain of the fine amplification subsystem to the selected fine gain value.

Method, system and apparatus for automatic gain control in direct-conversion receiver

A system and method for measuring integrated circuit (IC) temperature. An integrated circuit (IC) includes a thermal sensor and data processing circuitry. The thermal sensor utilizes switched currents provided to a reference diode and a thermal diode. The ratios of the currents provided to each of these diodes may be chosen to provide a given delta value between the resulting sampled diode voltages. At a later time, a different ratio of currents may be provided to each of these diodes to provide a second given delta value between the resulting sampled diode voltages. A differential amplifier within the data processing circuitry may receive the analog sampled voltages and determine the delta values. Other components within the data processing circuitry may at least digitize and store one or both of the delta values. A difference between the digitized delta values may calculated and used to determine an IC temperature digitized code.

Dynamic voltage reference for sampling delta based temperature sensor

A reference voltage generator is provided. In an example, the reference voltage generator includes a temperature-dependent device, a processing module configured to process a digital representations of first and second voltages derived from the temperature-dependent device and a reference voltage to determine a value, and a digital to analog converter (DAC) configured to generate a reference voltage based on the value. The first voltage is proportional to absolute temperature (PTAT) and the second voltage is complementary to absolute temperature (CTAT) and the reference voltage is substantially independent of absolute temperature in an operating temperature range of the reference voltage generator.

Self-calibrating digital bandgap voltage and current reference

A method and circuitry for determining a temperature-independent bandgap reference voltage are disclosed. The method includes determining a quantity proportional to an internal series resistance of a p-n junction diode and determining the temperature-independent bandgap reference voltage using the quantity proportional to an internal series resistance.

Auto-calibrating a voltage reference

The present invention provides embodiments of an apparatus that includes a pad configurable for connection to a voltage source that provides a first voltage and a buffer connected to the pad. The buffer includes a plurality of transistors that have nominal breakdown voltages that are less than the first voltage. The buffer is configured to maintain voltage differentials on the plurality of transistors that are less than the break-down voltage of the plurality of transistors during pull-down of a pad voltage from the first voltage to a selected low voltage level or during pull-up of the pad voltage from the selected low voltage level to the first voltage.

Complementary metal oxide semiconductor (CMOS) buffer

An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.

Method and apparatus for controlling a communication signal by monitoring one or more voltage sources

A circuit includes an input/output buffer circuit. The input/output buffer circuit includes an output buffer circuit and a bias control circuit. The output buffer circuit provides an output voltage in response to output information. The bias control circuit provides an output buffer bias voltage based on the output voltage.

Input/output buffer circuit

A method includes generating a first, second and third voltage output from a temperature sensing element of an integrated circuit using a respective, corresponding first, second and third, switched current source, for sequentially switching a respective first, second and third excitation current through the temperature sensing element. The third switched current source generates the corresponding third voltage output as a reference voltage between the first voltage and the second voltage. An error corrected difference is calculated between the first voltage and the second voltage using the reference voltage. In the method, the second excitation current is proportional to the first excitation current by a value n, and the third excitation current is proportional to the first excitation current by the square root of n.

Method and apparatus for integrated circuit temperature control

The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.

Method and apparatus for data inversion in memory device

An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be used to decode digital values to non-linear GAMMA corrected analog output voltages.

Reduced component digital to analog decoder and method

Various capacitors for use with integrated circuits and other devices and fabrication methods are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first capacitor plate that has at least two non-linear strips and forming a second capacitor plate that has a non-linear strip positioned between the at least two non-linear strips of the first capacitor plate. A dielectric is provided between the non-linear strip of the second capacitor plate and the at least two non-linear strips of the first capacitor plate.

Chip capacitor

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Markham, Canada

Grigori Temkine