International Business Machines Corporation

Other

Gregory William Alexander

Christian Jacobi

Brian David Barrick

Anthony Saporito

Jonathan T Hsieh

Timothy Carl Bronson

Aaron Tsai

Edward Thomas Malley

Jason D Kohl

Richard Joseph Branciforte

Brian Robert Prasky

Brian William Thompto

Khary J Alexander

Lee Evan Eisen

Deanna Postles Dunn Berger

David S Hutton

David Andrew Schroter

John Wesley Ward, Iii

Tu-An T Nguyen

James R Mitchell

Avery Francois

Chung-Lung K Shum

Balaram Sinharoy

James J Bonanno

Jang-Soo Lee

Somin Song

Winston Herring

Dung Q Nguyen

Fadi Y Busaba

David S Levitan

Brian William Curran

Gregory Miaskovsky

Eric M Schwarz

Steven R Carlough

Matthias Klein

Robert J Sonnelitter, Iii

Markus Kaltenbach

Bruce C Giamei

Adam B Collura

Craig Raymond Walters

Thomas Winters Fox

Ilya Granovsky

Michael Billeci

Eyal Naor

Guy G Tracy

Yair Fried

Ram Sai Manoj Bamdhamravuri

Ashraf ElSharif

Taylor J Pritchard

Stephen Duffy

Timothy John Slegel

William John Starke

Lisa Cranton Heller

Cedric Lichtenau

Michael F Fee

Phil C Yeh

Kenneth Lee Wright

Michael Andrew Blake

Vesselina K Papazova

Jane Helen Bartik

Kerstin Claudia Schelm

Shih-Hsiung Stephen Tung

Stefan Payer

Barry Watson Krumm

Wen H Li

Todd Alan Venton

David L Volk

Hieu Trong Huynh

Deanna P Berger

James Raymond Cuffney

Lawrence Joseph Powell, Jr

Milton Devon Miller, Ii

Akash V Giri

Michael P Mullen

Deanna P D Berger

Yossi Shapira

Avraham Ayzenfeld

Joshua M Weinberg

Olaf Knute Hendrickson

Scott Bruce Frommer

Anton Blanchard

Ophir Erez

Matthew Michael Garcia Pardini

Lior Binyamini

Steven D Goldenbogen

Shimon Ben-Yehuda

Chunggeon Rhee

Wesley J Ward, Iii

Juan Jose Arevalo

Robert Sonnelitter

A computer-implemented method for cache governance includes receiving, at a local cache of a processor chip, a first fetch request for data for a cache line of the local cache. The method further includes allocating a first cache controller to allow the first fetch request to receive the data and to track reception of the data. The method further includes receiving, at the local cache of the processor chip, a second fetch request for the data for the cache line of the local cache. The method further includes determining via an address compare logic associated with the local cache whether the first fetch request in the first cache controller is for a same cache line that the second fetch request is targeting. The method further includes allowing the second fetch request to allocate a second cache controller and copying metadata from the first cache controller to the second cache controller.

Cache governance in a computing environment with multiple processors

In an approach, responsibility for reissuing a fetch micro-operation is allocated to a reissue queue subsequent to a cache miss corresponding to a cache and the fetch micro-operation. Responsive to higher level cache returning data to the cache, an issue selection algorithm of the issue queue is overridden to prioritize reissuing the fetch micro-operation.

Load reissuing using an alternate issue queue

Embodiments are for using a decentralized hot cache line tracking fairness mechanism. In response to receiving an incoming request to access a cache line, a determination is made to grant access to the cache line based on a requested state and a serviced state used for maintaining the cache line, a structure comprising the requested and serviced states. In response to the determination to grant access to the cache line, the requested state and the serviced state are transferred along with data of the cache line.

Decentralized hot cache line tracking fairness mechanism

A node of the computing environment obtains an exclusive fetch request of a cache line shared by, at least, the node and a manager node of the computing environment. The exclusive fetch request includes a state indication regarding processing of the exclusive fetch request by the manager node. The node processes the exclusive fetch request, based on the state indication included with the exclusive fetch request regarding processing of the exclusive fetch request by the manager node.

Invalidity protection for shared cache lines

A computer system includes a processor core and a memory system in signal communication with the processor core. The memory system includes a first cache and a second cache. The first cache is arranged at a first level of a hierarchy in the memory system and is configured to store a plurality of first-cache entries. The second cache is arranged at a second level of the hierarchy that is lower than the first level, and stores a plurality of second-cache entries. The first cache maintains a directory that contains information for each of the first-cache entries. The second cache maintains a shadow pointer directory (SPD) that includes one or more SPD entries that maps each of the first-cache entries to a corresponding second cache entry at a lower-level cache location.

Shadow pointer directory in an inclusive hierarchical cache

A method for managing designated authority status in a cache line includes identifying an initial designated authority (DA) member cache for a cache line, transferring DA status from the initial DA member cache to a new DA member cache, determining whether the new DA member cache is active, indicating a final state of the initial DA cache responsive to determining that the new DA member cache is active, and overriding a DA state in a cache control structure in a directory. A method for managing cache accesses during a designated authority transfer includes receiving a designated authority (DA) status transfer request, receiving an indication that a first cache will invalidate its copy of the cache line, allowing a second cache to assume DA status for the cache line, and denying access to the first cache's copy of the cache line until invalidation by the first cache is complete.

Final cache directory state indication

A computer-implemented method is provided. The method includes determining whether a rejection of a request is required and determining whether the request is software forward progress (SFP)-likely or SFP-unlikely upon determining that the rejection of the request is required. The method also includes executing a first pseudo random decision to set or not set a requested state of the request in an event the request is SFP-likely or SFP-unlikely, respectively, and rejecting the request following execution of the second pseudo random decision.

Hot line fairness mechanism favoring software forward progress

To facilitate an efficient processing of contended cache lines, a cache controller that is associated with a requestor receives a fetch request for data from the requestor. The fetch request is associated with a cache scope designation. If the data is in a high-level cache (e.g., L1 cache) associated with the requestor, the cache controller returns the requested data to the requestor. If the data is not in the high-level cache or if the data is not within the cache pool identified by the cache scope of search designation, and/or if obtaining the data is contentious, the controller returns a cache miss, undeliverable data, and request done instruction to the requestor. Such scheme allows or permits address contention events when the requestor deems such events are necessary and/or when important. As such, address contention events, performance, latencies, increased executions times, inefficient use of resources, may be diminished.

Cache management using cache scope designation

Embodiments are for preemptive tracking of remote requests for decentralized hot cache line fairness tracking. Authority is requested for a cache line in conjunction with querying for outstanding requests for the cache line. One or more responses are received regarding the outstanding requests for the cache line. In response to receiving the one or more responses regarding the outstanding requests and in advance of receiving the authority for the cache line, the outstanding requests are preemptively tracked in a requested structure associated with the cache line.

Preemptive tracking of remote requests for decentralized hot cache line fairness tracking

A primary controller has authority of a cache line associated with a fetch and manages a second cache line request from a different and non-associated secondary requesting entity. A secondary controller, associated with the secondary requesting entity, is granted authority of the cache line and further manages multiple subsequent simultaneous or overlapping requests for the cache line from different non-associated subsequent requesting entities by maintaining authority of the cache line, by granting read-only access to the cache line to respective subsequent controllers, each associated with a different subsequent requesting entity, and by passing a non-authority token to each of the respective subsequent controllers.

Multiprocessor system cache management with non-authority designation

A method and a computer system for core recovery management are provided. A first operation signal is generated via a first hardware agent. The first operation signal indicates that the first hardware agent is processing an operation requested by a first processor core. The first processor core receives a first extend fence signal based on the generated first operation signal. As long as the first extend fence signal is received via the first processor core, the first processor core is kept in a fenced state for core recovery.

Preventing extraneous messages when exiting core recovery

Embodiments are for special tracking pool enhancement for core L1 address invalidates. An invalidate request is designated to fill an entry in a queue in a local cache of a processor core, the queue including a first allocation associated with processing any type of invalidate request and a second allocation associated with processing an invalidate request not requiring a response in order for a controller to be made available, the entry being in the second allocation. Responsive to designating the invalidate request to fill the entry in the queue in the local cache, a state of the controller that made the invalidate request is changed to available based at least in part on the entry being in the second allocation.

Special tracking pool enhancement for core local cache address invalidates

Aspects of the invention include defining one or more processor units having a plurality of caches, each processor unit comprising a processor having at least one cache, and wherein each of the one or more processor units are coupled together by an interconnect fabric, for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class comprises a chronology vector, arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, determining a first cache line to evict based on the chronology vector, and determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.

Lateral persistence directory states

Aspects of the invention include computer-implemented methods, systems, and computer program products that access a multi-copy scope directory state of a cache memory that indicates a scope of sharing of a cache line in a cache memory system and determine a scope of sharing of the cache line in the cache memory system based on the multi-copy scope directory state, where the multi-copy scope directory state enumerates a plurality of scopes within the cache memory system. The scope of sharing is used to reduce a number of queries to one or more cache memories having a larger scope than a shared scope identified in the scope of sharing. The multi-copy scope directory state of the cache memory is updated based on detecting a change in shared scope of the cache line within the cache memory system.

Multiple copy scoping bits for cache memory

A multi-slice processor comprising a high-level structure and history buffer. Write backs are no longer associated with the history buffer and the history buffer comprises slices determined by logical register allocation. The history buffer receives a register pointer entry and either releases or restores the entry with functional units comprised in the history buffer.

Slice-based allocation history buffer

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Pflugerville, TX, United States of America

Gregory William Alexander