Lsi Logic Corporation

Lsi Corporation

Gregory William Achilles

William J Schmitz

Gordon Keith Grimes

G Keith Grimes

Methods and systems assess timing of PCI signals. A test mode is initiated within a host adapter board. A clock signal is generated for the host adapter board. PCI signals are generated within the host adapter board. One or more PCI signal lines of the host adapter board are electronically selected; and timing (e.g., slew rate and/or clock-to-signal valid) of the one or more PCI signal lines is assessed.

Systems and methods for assessing timing of PCI signals

Systems and methods for testing data lines to determine signal degradation in the data lines. A system includes a signal generator for generating a test pattern and for transferring the test pattern through the data lines. The system also includes an analyzer communicatively connected to the data lines to determine degradation of the test pattern in the data lines. The signal generator generates and transfers a first test pattern through the data lines. The first test pattern includes a first portion having a first polarity and a second portion having a second polarity. The signal generator then generates and transfers a second test pattern through the data lines in response to transferring the first test pattern. The test patterns may be repeated one or more times to determine cross talk caused by inductive coupling between data lines and additive reflections.

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Colorado Springs, CO, United States of America

Gregory William Achilles