Hewlett-Packard Company

Gregory T Sullivan

Robert H Grant

David Book

Bent Stoevhase

Robin Purohit

A fiber optic switch interconnects fiber optic channels so that a fiber optic network can be implemented. Channel modules provide ports (p1-pi) for connection of the fiber optic channels. Each channel module has a receive memory for temporarily storing incoming data frames from the fiber optic channels associated therewith. A switch module having a data distribution network interconnects each of the channel modules and permits ultimate connection of a source channel to a destination channel. A path allocation system, which controls the switch module, allocates the data paths between the channels. The path allocation system has a scheduler which maintains a destination queue (Q.sub.p1 -Q.sub.pi) for each of the channels, a sentry which determines when a new data frame is ready to be routed, and an arbitrator which arbitrates port availability and which grants transfer requests proposed by the scheduler.

High performance path allocation system and method for a fiber optic

A frame time monitoring system tracks the time in which data frames reside within a fiber optic switch for a fiber optic network. The network switch transfers data frames from source ports to destination ports. The frame time monitoring system comprises a digital signal processor (DSP), which is configured by a software program to implement a plurality of timers relative to frames to be routed through the switch from a source port to a destination port. The processor operates as an incrementer and is configured to output a series of sequential timer states corresponding to each particular frame. The timer states are generally indicative of the amount of time in which the frame has resided in the switch. A logic network of logic gates is connected to the processor to receive and interpret the timer states. The logic network has frame busy (FBSY) and delete mechanisms for determining elapse of respective FBSY and delete time periods based upon the timer states. The FBSY and delete mechanisms generate respective FBSY and delete signals after the elapse of the periods, which can vary for optimization reasons depending upon frame class and type. Thus, in the foregoing configuration, a processor is utilized as a timing incrementer and logical decisions are allocated to the logic network, resulting in an optimum balance between hardware and software so as to minimize cost, space requirements, and complexity, and maximize frame tracking resolution.

High performance frame time monitoring system and method for a fiber

A fiber optic switch interconnects fiber optic channels so that a fiber optic network can be implemented. Channel modules provide ports (p1-pi) for connection of the fiber optic channels. Each channel module has a receive memory for temporarily storing incoming data frames from the fiber optic channels associated therewith. A switch module having a data distribution network interconnects each of the channel modules and permits ultimate connection of a source channel to a destination channel. A path allocation system, which controls the switch module, allocates the data paths between the channels. The path allocation system has a scheduler which maintains a destination queue (Q.sub.p1 -Q.sub.pi) for each of the channels, a sentry which determines when a new data frame is ready to be routed, and an arbitrator which arbitrates port availability and which grants transfer requests proposed by the scheduler. Significantly, the arbitrator is equipped with fairness insurance mechanisms for insuring that transfer requests are always timely and efficiently serviced.

Growing community of inventors

Brampton, Canada

Gregory T Sullivan