Compaq Computer Corporation, Inc.

Gregory T Chandler

Ryan A Callison

William J Walker

Dale J Mayer

Michael L Witkowski

Gary B Kotzur

Thomas W Grieff

Mohammad A Khan

William C Galloway

A network switch includes a plurality of first network ports coupled to a first bus, a plurality of second network ports coupled to a second bus, a bridge interface enabling data transfer between the buses, a switch manager controlling the flow of network data, and a processor for performing supervisory and control functions. The first and second network ports operate according to different network protocols, and the first and second buses operate according to different bus standards. During packet data transfers across the first bus, the bridge interface emulates a first network port. During packet data transfers across the second bus, the bridge interface primarily acts as a slave to the second network ports by storing control lists for execution by the second network ports, thus relieving the processor of performing overhead functions associated with data transfers across the second bus.

Network switch with a multiple bus structure and a bridge interface for transferring network data between different buses

A network switch including a plurality of first network ports, a plurality of second network ports, a first bus, a second bus and a bridge interface coupled between the first and second buses. The first ports receive and transmit network data according to a first network protocol and the second ports receive and transmit network data according to a second network protocol. The first and second buses operate according to different bus standards. The bridge interface enables data transfer between the first and second buses and thus between the networks operating at different protocols. The switch includes a switch manager that controls the flow of network data and a processor for performing supervisory and control functions. The bridge interface includes receive buffers and transmit buffers assigned to respective ports. During packet data transfer operations across the first bus, the bridge interface emulates a first network port. During packet data transfer operations across the second bus, the bridge interface primarily acts as a slave to the second network ports by storing control lists for execution by the second network ports. This processor is relieved of performing necessary overhead functions associated with the second bus and is thus freed to perform other important switch functions.

Network switch with a multiple bus structure and a bridge interface for

A bridge for coupling two buses together utilizes a data buffer to act as a point of synchronization to provide effective data operations between the buses. The bridge includes master and slave capability on both buses and an arbiter for selecting between requests from bus masters on one bus. The data buffer includes a number of dual ported memories for write posting and read ahead operations. Each dual ported memory is allocated to a bus master of the one bus. The bridge allows data operations to each dual ported memory based on data or space availability of the memory. Simultaneous reading and writing capability on alternate buses is provided.

Bridge having a data buffer for each bus master

A bridge for coupling two buses together utilizes a data buffer to act as a point of synchronization to provide effective data operations between the buses. The data buffer includes a number of dual ported memories for write posting and read ahead operations. The data buffer further includes address incrementing and comparison circuitry to synchronize the flags into the clock domain of each bus.

Apparatus and method for synchronously providing a fullness indication

A disk array controller board which utilizes an EISA bus master which is a slave on its internal data bus to allow an advanced drive array controller chip (ADAC) to operate as a master. The ADAC is connected to transfer buffer RAM. The protocol of the internal data bus provides for a cycle to load a host memory address into the bus slave, to provide transfer count information and slave specific information and for a series of data transfer cycles. The local processor is connected to the EISA bus master and the ADAC to control operations and to provide certain information. The ADAC is controlled by structures referred to as command descriptor blocks (CDBs). Each CDB includes information which describes the various addresses, control bits and functional bits used by the ADAC to perform its transfer operations. The local processor directly writes and deposits data forming a CDB into the transfer buffer RAM. The ADAC obtains the CDB, loads the data into registers and then performs operations according to the information contained in these registers until a transfer is done. The ADAC itself performs operations, including automatic stripe scattering and gathering to develop contiguous host memory fields from striped array data. A series of CDBs can be chained so that a complex series of tasks can be developed. In one variation a string of CDBs is developed to transfer data but some data is transferred to the bit bucket, while other data is actually transferred.

Disk array controller having internal protocol for sending

A disk array controller board which utilizes an EISA bus master which is a slave on its internal data bus to allow an advanced drive array controller chip (ADAC) to operate as a master. The ADAC is connected to transfer buffer RAM. The protocol of the internal data bus provides for a cycles to load a host memory address into the bus slave, to provide transfer count information and slave specific information and for a series of data transfer cycles. The local processor is connected to the EISA bus master and the ADAC to control operations and to provide certain information. The ADAC is controlled by structures referred to as command descriptor blocks (CDBs). Each CDB includes information which describes the various addresses, control bits and functional bits used by the ADAC to perform its transfer operations. The local processor directly writes and deposits data forming a CDB into the transfer buffer RAM. The ADAC obtains the CDB, loads the data into registers and then performs operations according to the information contained in these registers until a transfer is done. The ADAC itself performs operations, including automatic stripe scattering and gathering to develop contiguous host memory fields from striped array data. A series of CDBs can be chained so that a complex series of tasks can be developed. In one variation a string of CDBs is developed to transfer data but some data is transferred to the bit bucket, while other data is actually transferred.

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Houston, TX, United States of America

Gregory T Chandler