Psemi Corporation

Allegro Microsystems, LLC

Murata Manufacturing Co., Ltd.

Arctic Sand Technologies, Inc.

Peregrine Semiconductor Corporation

Maxim Integrated Products, Inc.

Allergo Microsystems, LLC

Artic Sand Technologies, Inc.

Gregory Szczeszynski

David M Giuliano

Aichen Low

Oscar Blyde

Jeff Summit

Raymond Barrett, Jr

Tim Wen Hui Yu

Gary Chunshien Wu

Vijay Mangtani

Bassem Alnahas

Brian Zanchi

Pranav Raval

Buddhika Abesingha

Walid Fouad Mohamed Aboueldahab

Nai-Chi Lee

Antony Christopher Routledge

Chak Sang Ngai

Shashank Wekhande

Satish Kumar Vangara

Matthew Szaniawski

Xiaowu Sun

Gerardo A Monreal

Jean-Marc Roger Mourant

David Toebes

George P Humphrey

Arezu Bagheri

Jeffrey Summit

Mauricio Contaldo

Bassem AINahas

David Guiliano

An apparatus for providing electric power to a load includes a power converter that accepts electric power in a first form and provides electric power in a second form. The power converter comprises a control system, a first stage, and a second stage in series. The first stage accepts electric power in the first form. The control system controls operation of the first and second stage. The first stage is either a switching network or a regulating network. The second stage is a regulating circuit when the first stage is a switching network, and a switching network otherwise.

Switched-capacitor power converters

An integrated circuit (IC) for controlling a power converter. The IC includes a controller that, in a first sensing period, enables a sensing circuit of the power converter and electrically connects an output node of an op amp of the sensing circuit and a first node of a capacitor of the sensing circuit, creating a first voltage across the capacitor; in a period between the first sensing period and a second sensing period, disables the sensing circuit and disconnects the output node of the op amp and the first node of the capacitor to maintain the first voltage across the capacitor; and in the second sensing period, enables the sensing circuit and connects the output node of the op amp and the first node of the capacitor, the maintained first voltage across the capacitor reducing a settling time for the enabled sensing circuit.

Systems, methods, and devices for current sensing

Circuits and methods that enable a 'break-before-make' process for an electronic switch that avoids the relatively large time delays of fixed time delay circuitry. Logic gates, rather than a time delay, are used to lock out an input switch through-path from turning ON before another input switch through-path is fully turned OFF. An embodiment includes a first and second monitor logic blocks, configured such that (1) a first through-path is turned OFF before a first shunt-path is allowed to turn ON and before a second shunt-path is allowed to turn OFF, and the second shunt-path is turned OFF before a second through-path is allowed to turn ON; and (2) the second through-path is turned OFF before the second shunt-path is allowed to turn ON and before the first shunt-path is allowed to turn OFF, and the first shunt-path is turned OFF before the first through-path is allowed to turn ON.

Voltage supply switch interlock logic

Circuit embodiments for a switched-capacitor power converter, and/or methods of operation of such a converter, that robustly deal with various startup scenarios, are efficient and low cost, and have quick startup times to steady-state converter operation. Embodiments prevent full charge pump capacitor discharge during shutdown of a converter and/or rebalance charge pump capacitors during a startup period before switching operation by discharging and/or precharging the charge pump capacitors. Embodiments may include a dedicated rebalancer circuit that includes a voltage sensing circuit coupled to an output voltage of a converter, and a balance circuit configured to charge or discharge each charge pump capacitor towards a target steady-state multiple of the output voltage of the converter as a function of an output signal from the voltage sensing circuit indicative of the output voltage. Embodiments prevent or limit current in-rush to a converter during a startup state.

Startup of switched capacitor step-down power converter

In a power converter that includes a switched-capacitor circuit connected to a switched-inductor circuit, reconfiguration logic causes the switched-capacitor circuit to transition between first and second switched-capacitor configurations with different voltage-transformation ratios. A compensator compensates for a change in the power converter's forward-transfer function that would otherwise result from the transition between the two switched-capacitor configurations.

Pole compensation in reconfigurable power converter

A circuit suitable for use with a multi-level power converter cell that (1) charges boot capacitors at startup to a sufficient level to power level shifters and drivers that control the power switches within the cell, (2) pre-charges each fly capacitor to a target voltage, (3) provides a shut-down and/or a standby mode of operation that enables a quick re-start of operation, and (4) balances fly capacitor voltages when the fly capacitor(s) is/are not actively charge-balanced. One embodiment includes a first switchable current source coupled between a fly capacitor and an input voltage; a second switchable current source coupled between the fly capacitor and a reference potential; and a third switchable current source coupled in parallel with the fly capacitor; wherein the switchable current sources are configured to charge the fly capacitor in a first mode of operation, and to discharge the fly capacitor in a second mode of operation.

Circuits and methods to startup and shutdown multi-level converters

Circuits and methods that limit current through power FETs of power converter to reduce damaging current in-rush events, independent of switching frequency, device mismatches, and PVT variations. Embodiments utilize a closed-loop feedback circuit and/or a calibrated compensation circuit to regulate, substantially independent of frequency, the control voltage Vapplied to a power FET gate. In a reduced gate-drive mode, connecting a feedback or compensation circuit to the gate of an LDO source-follower FET allows the gate voltage to be regulated to control the LDO output voltage to a final inverter coupled to the gate of a power FET so that Vis adjusted to provide a reduced gate-drive to the power FET; connecting to the output of the LDO allows the LDO output voltage to the final inverter to be directly regulated to adjust V; connecting to the gate of the power FET allows Vto be directly set.

Accurate reduced gate-drive current limiter

Circuits and methods for sensing output current of a power converter, controlling output current in multiple parallel power converters, and enabling reconfigurability of output control for multiple parallel power converters. One embodiment includes a current sensing circuit configured to be coupled to a power converter, the current sensing circuit configured to receive a first voltage representative of an output current of the power converter and output a low-frequency filtered second voltage based on the first voltage and a high-frequency filtered third voltage based on the first voltage. In some embodiments, the first voltage is generated by sensing an output current of the power converter and converting the sensed output current to the first voltage. Other embodiments include a plurality of power stages and corresponding current sensing circuits, wherein the outputs of the low-frequency filters of the current sensing circuits are coupled in common.

Power converter with integrated multi-phase reconfigurable current balancing

In a power converter having a regulator and charge pump, both of which operate in plural modes, a controller receives information indicative of the power converter's operation and, based at least in part on said information, causes transitions between regulator modes and transitions between charge-pump modes.

Adaptive control for reconfiguring a regulator and/or a charge pump for a power converter

An apparatus for converting a first voltage into a second voltage includes a reconfigurable switched capacitor power converter having a selectable conversion gain. The power converter has switch elements configured to electrically interconnect capacitors to one another and/or to the first or second voltage in successive states. The switch elements are configured to interconnect at least some capacitors to one another through the switch elements. A controller causes the reconfigurable switched capacitor power converter to transition between first and second operation modes. The controller minimizes electrical transients arising from transition between modes. In the first operating mode, the power converter operates with a first conversion gain. In the second operating mode, it operates with a second conversion gain.

Charge adjustment techniques for switched capacitor power converter

Circuits and methods for protecting a multi-level power converter using no more than two high-voltage FET switches while allowing all or most other power switches to be low-voltage FET switches. Some embodiments provide protective high-voltage top and bottom FETs designed to saturate before the remaining low-power FET switches saturate. Other embodiments may use only low-power FETs for the power switches but provide protective circuits configured to be in an always-ON (conducting) state when in normal power conversion operation, and to quickly switch to an OFF (non-conducting) state in the event of transients or a fault condition. Optionally, one or more of the protective circuits may be used in a controlled manner to limit or block current flow during certain types of fault conditions and/or to limit in-rush current during startup of a power converter.

Power converter

An apparatus includes first and second pluralities of switches, a controller for controlling these switches, gate-drivers for driving switches from the first plurality of switches, and first and second terminals configured for coupling to corresponding first and second external circuits at corresponding first and second voltages. During operation, the controller causes the first plurality of switches to transition between states. These transitions result in the second voltage being maintained at a value that is a multiple of the first voltage. The controller also causes the second plurality of switches to transition between states. These transitions resulting in capacitors being coupled or decoupled from the second voltage. The gate drivers derive, from the capacitors, charge for causing a voltage that enables switches from the first plurality of switches to be driven.

Power supply for gate driver in switched-capacitor circuit

Multi-level DC-to-DC converter circuits and methods that permit a full range of output voltages, including near and at zone boundaries. Embodiments alternate among adjacent or near-by zones, operating in a first zone for a selected time and then in a second zone for a selected time. Embodiments may include a parallel capacitor voltage balancing circuit that connects a capacitor to a source voltage to charge that capacitor, or couples two or more capacitors together to transfer charge, all under the control of real-time capacitor voltage measurements. Embodiments may include a lossless voltage balancing solution where out-of-order state transitions are allowed, thus increasing or decreasing the voltage across specific capacitors to prevent voltage overstress on the converter main switches. Restrictions may be placed on the overall sequence of state transitions to reduce or avoid transition state toggling, allowing each capacitor an opportunity to have its voltage steered as necessary for balancing.

Multi-level DC-DC converter

Circuits and methods that solve the light-load problem of a multi-level converter by generating a ripple signal in the control loop of the multi-level converter that causes a large output current ripple during light load conditions. This added current ripple does not change the average output current but does create a temporary positive and negative current that can be used to balance and charge/discharge the fly capacitors of the multi-level converter. An alternative approach is to add extra switching cycles for the fly capacitors when the output ripple current crosses zero.

Light-load recovery in a multi-level converter

Disclosed embodiments may include a power converter system with fault handling. Embodiments may include first and second power converters each including an output terminal and a control terminal, the first and second power converters to regulate voltage or current at their respective output terminals based on a voltage at their respective control terminals, the output terminals coupled to each other, and the control terminals coupled to each other; wherein the first power converter comprises: a circuit to detect a fault condition associated with the first power converter and to generate a first fault signal at the control terminal of the first power converter after the detecting the fault condition associated with the first power converter; wherein the second power converter comprises: a circuit to change an operating mode of the second power converter after generating the first fault signal at the control terminal of the first power converter.

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Hollis, NH, United States of America

Gregory Szczeszynski