Hewlett-Packard Development Company, L.p.

Hewlett-Packard Company

Hewlett Packard Enterprise Development LP

Robert Zeidman

Gregory Stuart Snider

Philip John Kuekes

Richard Stanley Williams

Duncan R Stewart

Warren J Robinett

Shih-Yuan Wang

Raymond G Beausoleil

Alexandre M Bratkovski

Wei Guang Wu

Wei E Wu

Ron M Roth

Zhaoning Yu

Robert Marc Zeidman

Richard J Carter

Dmitri Borisovich Strukov

J Barry Shackleford

Joseph Straznicky

Phillip J Kuekes

Warren Robinett

Stanley R Williams

Gadiel Seroissi

Piecewise smooth regularization of data is disclosed. One example is a system where input data is received, the input data being associated with a certainty function indicative of confidence of each data element in the input data. Guide data including information indicative of presumed piecewise smoothness of the input data is received. A joint edge-aware filter is applied, based on the guide data, to the input data to provide filtered data. The joint edge-aware filter is applied, based on the guide data, to the certainty function to provide filtered certainty. A normalized convolution algorithm is applied to the filtered data and the filtered certainty to provide output data indicative of a piecewise smooth regularization of the input data.

Piecewise smooth regularization of data

Methods and system for modeling the behavior of binary synapses are provided. In one aspect, a method of modeling synaptic behavior includes receiving an analog input signal and transforming the analog input signal into an N-bit codeword, wherein each bit of the N-bit codeword is represented by an electronic pulse. The method includes loading the N-bit codeword into a circular shift register and sending each bit of the N-bit codeword through one of N switches. Each switch applies a corresponding weight to the bit to produce a weighted bit. A signal corresponding to a summation of the weighted bits is output and represents a synaptic transfer function characterization of a binary synapse.

Systems and methods for modeling binary synapses

A method for implementing an artificial neural network includes connecting a plurality of receiving neurons to a plurality of transmitting neurons through memristive synapses. Each memristive synapse has a weight which is initialized into a conductive state. A binary input vector is presented through the memristive synapses to the plurality of receiving neurons and the state of one or more of the memristive synapses modified based on the binary input vector.

Memristive adaptive resonance networks

A three-dimensional integrated circuit comprising a submicroscale integrated-circuit substrate and n nanoscale layers stacked above the submicroscale integrated-circuit substrate, a nanowire-junction memory element in each of which is independently controlled by two submicroscale subcomponents within the submicroscale integrated-circuit substrate, the first submicroscale subcomponent coupled through a first set of switches to each of the n nanowire-junction memory elements and the second submicroscale subcomponent coupled through a second set of switches to each of the n nanowire-junction memory elements, the total number of switches in the first and second sets of switches less than 2n, and n greater than or equal to 2.

Three-dimensional integrated circuit

A method for operating a circuit () containing memristive devices () senses respective states of a plurality of memristive devices () and refreshes the respective states of the memristive devices () according to the states sensed. A memristive device () including an array of memristive devices () between crossing lines (and) includes logic that senses respective states of memristive devices () and refreshes the respective states of the memristive devices () according to the states sensed.

Refreshing memristive systems

A capacitive crossbar array includes a first set of conductors and a second set of conductors which intersect to form crosspoints. A nonlinear capacitive device is interposed between a first conductor within the first set and a second conductor within the second set at a crosspoint. The nonlinear capacitive device is configured to store information which is accessible through said first conductor and said second conductor. A method for utilizing a capacitive crossbar array is also provided.

Capacitive crossbar arrays

One embodiments of the present invention is directed to a single-bit memory cell comprising transistor-based bit latch having a data state and a memristor, coupled to the transistor-based bit latch, in which the data state of the transistor-based bit latch is stored by a store operation and from which a previously-stored data state is retrieved and restored into the transistor-based bit latch by a restore operation. Another embodiment of the present invention is directed to a single-bit memory cell comprising a master-slave flip flop and a slave flip flop, and a power input, a memristor, a memory-cell power input, a first memory-cell clock input, a second memory-cell clock input, a memory-cell data input, a memory-cell data output, and two or more memory-cell control inputs.

Non-volatile data-storage latch

Embodiments of the present invention include hybrid microscale-nanoscale neuromorphic integrated circuits that include an array of analog computational cells fabricated on an integrated-circuit-substrate. The analog electronic circuitry within each computational cell connected to one or more pins of a first type and to one or more pins of a second type that extend approximately vertically from the computational cells. The computational cells are additionally interconnected by one or more nanowire-interconnect layers, each nanowire-interconnect layer including two nanowire sublayers on either side of a memristive sublayer, with each nanowire in each nanowire sublayer of an interconnect layer connected to a single computational-cell pin and to a number of nanowires in the other nanowire sublayer of the interconnect layer.

Hybrid microscale-nanoscale neuromorphic integrated circuit

Various method and system embodiments of the present invention are directed to implementing serial logic gates using nanowire-crossbar arrays with spintronic devices located at nanowire-crossbar junctions. In one embodiment of the present invention, a nanowire-crossbar array comprises a first nanowire and a number of substantially parallel control nanowires positioned so that each control nanowire overlaps the first nanowire. The nanowire-crossbar array includes a number of spintronic devices. Each spintronic device is configured to connect one of the control nanowires to the first nanowire and operate as a latch for controlling signal transmissions between the control nanowire and the first nanowire.

Methods and systems for implementing logic gates with spintronic devices located at nanowire crossbar junctions of crossbar arrays

A computing system for implementing at least one electronic circuit with gain comprises at least one two-dimensional molecular switch array. The molecular switch array is formed by assembling two or more crossed planes of wires into a configuration of devices. Each device comprises a junction formed by a pair of crossed wires and at least one connector species that connects the pair of crossed wires in the junction. The junction has a functional dimension in nanometers, and includes a switching capability provided by both (1) one or more connector species and the pair of crossed wires and (2) a configurable nano-scale wire transistor having a first state that functions as a transistor and a second state that functions as a conducting semiconductor wire. Specific connections are made to interconnect the devices and connect the devices to two structures that provide high and low voltages.

Configurable molecular switch array

Embodiments of the present invention are employ dynamical, nanoscale devices, including memristive connections between nanowires, for constructing parallel, distributed, dynamical computational networks and systems, including perceptron networks and neural networks. In many embodiments of the present invention, neuron-like computational devices are constructed from silicon-based microscale and/or submicroscale components, and interconnected with one another by dynamical interconnections comprising nanowires and memristive connections between nanowires. In many massively parallel, distributed, dynamical computing systems, including the human brain, there may be a far greater number of interconnections than neuron-like computational nodes. Use of dynamical nanoscale devices for these connections results in enormous design, space, energy, and computational efficiencies.

Computational nodes and computational-node networks that include dynamical-nanodevice connections

Software that modifies the source code for readily available software tasks&#x2014;typically applications and hardware drivers&#x2014;so that a small, fast, reliable operating system can be synthesized to control execution of these readily available software tasks.

Using readily available driver and application source code with a synthesized operating system

Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. A method is provided for fabricating a nanoscale/microscale interface having a microscale layer and a predominantly nanoscale layer.

Mixed-scale electronic interface

Various embodiments of the present invention are directed to three-dimensional crossbar arrays. In one aspect of the present invention, a three-dimensional crossbar array includes a plurality of crossbar arrays, a first demultiplexer, a second demultiplexer, and a third demultiplexer. Each crossbar array includes a first layer of nanowires, a second layer of nanowires overlaying the first layer of nanowires, and a third layer of nanowires overlaying the second layer of nanowires. The first demultiplexer is configured to address nanowires in the first layer of nanowires of each crossbar array, the second demultiplexer is configured to address nanowires in the second layer of nanowires of each crossbar array, and the third demultiplexer is configured to supply a signal to the nanowires in the third layer of nanowires of each crossbar array.

Three-dimensional crossbar array systems and methods for writing information to and reading information stored in three-dimensional crossbar array junctions

Various embodiments of the present invention are directed to photonic-interconnection-based compute clusters that provide high-speed, high-bandwidth interconnections between compute cluster nodes. In one embodiment of the present invention, the compute cluster includes a photonic interconnection having one or more optical transmission paths for transmitting independent frequency channels within an optical signal to each node in a set of nodes. The compute cluster includes one or more photonic-interconnection-based writers, each writer associated with a particular node, and each writer encoding information generated by the node into one of the independent frequency channels. A switch fabric directs the information encoded in the independent frequency channels to one or more nodes in the compute cluster. The compute cluster also includes one or more photonic-interconnection-based readers, each reader associated with a particular node, and each reader extracting the information encoded in the independent frequency channels directed to the node for processing.

Growing community of inventors

Mountain View, CA, United States of America

Gregory Stuart Snider