University of Notre Dame Du Lac

Indiana Integrated Circuits, LLC

Gregory Snider

Jason M Kulick

Tian Lu

Alexei Orlov

Rene Celis-Cordova

In a method computer storage element operation, first and second rising (or falling) clock edges are applied to first and second power inputs of the computer storage element having a transistor array between the first and second power inputs over time Twhereupon a logic value applied to an input of the transistor array is stored therein. Thereafter, first and second falling (or rising) clock edges are applied to the first and second power inputs over time T, whereupon part of an electrical charge or energy associated with the logic value stored in the transistor array is provided to circuitry that generates the first and/or second clock edge(s), wherein the value(s) of time Tand/or time Tis/are greater than a product of RC, where R is resistance associated with the computer storage element, and C is a load capacitance associated with the computer storage element.

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Niles, MI, United States of America

Gregory Snider