Google Inc.

Gregory Sizikov

Mikhail Popovich

Shuai Jiang

Houle Gan

Chee Yee Chung

Cornelius Bendict O'Sullivan

WeiFeng Pan

Madhusudan K Iyengar

Xin Li

Yuan Hang Li

Thomas James Norrie

Teckgyu Kang

Woon-Seong Kwon

Shawn Emory Bender

Jorge Padilla

Melanie Beauchemin

Georgios K Konstadinidis

Zuowei Shen

Woon Seong Kwon

Federico Pio Centola

Richard Roy

Craig Kaneshiro

Mark Villegas

Mark Omernick

Xu Gao

The disclosure relates to power modules that include elevated inductors with capacitors disposed under the inductors. In one aspect, a power module includes a first circuit board having a first surface and a second surface opposite the first surface. One or more inductors are mounted on the first surface. Each of the one or more inductors includes a top surface and a bottom surface opposite the top surface and that faces the first surface of the first circuit board. Each inductor is elevated above the first surface of the first circuit board such that at least a portion of the bottom surface of the inductor does not contact the first surface of the first circuit board. The first circuit board includes capacitors arranged in an area below the portion of the bottom surface of the inductor that does not contact the first surface of the first circuit board.

Power modules with elevated inductors and capacitors arranged under the inductors

A system contains a machine learning application specific integrated circuit (ASIC) and a power supply unit. The power supply unit and the ASIC are configured to be in data communication through dedicated pins on the ASIC and the power supply unit. The power supply unit detects a present power consumption of the ASIC. Upon determining that a threshold condition has been met, the power supply unit, responsive to the condition sends a digital signal to the ASIC. The ASIC contains a synchronizer which synchronizes the digital signal to be consistent with the ASICs internal clock frequency. A chip manager the synchronized signal and other signals to generate a throttling mask. The throttling mask is sent to a sequencer of the ASIC, which then limits the instruction flow into the processing units of the ASIC based on the mask. This in turn limits the power being consumed by the ASIC.

Power throttling mechanism using instruction rate limiting in high power machine-learning ASICs

An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connecter of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.

Power sequencing in an active silicon interposer

Systems and methods for resonance aware performance management of processing devices. In one aspect, a method includes iteratively testing a performance operation for the processing device, wherein each iteration is performed at an iteration voltage level for a power delivery network. The performance operation is applied at different application periods and at the iteration voltage level for the iteration. If no failure condition is met, the iteration voltage is reduced and another iteration is done. Upon a failure occurring at a particular application period, an operational voltage level for the power delivery network that is based on the iteration voltage level for the iteration in which a failure condition was induced is selected, and application of the performance operation at the particular application period is precluded.

Resonance aware performance management

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for monitoring energy consumption. In one aspect, a method includes sending, to a power monitor of a circuit board, requests for power consumption data. The requests are sent periodically based on a reference clock that is located external to the circuit board and that is more accurate than a clock of the power monitor. Each request is for an accumulated amount of power for components of the circuit board. In response to each request, power consumption data is received from the power monitor. The power consumption data specifies the accumulated amount of power for the components of the circuit board since a previous request sent to the circuit board. An amount of energy consumed by the components of the circuit board over a time period is determined based on the received power measurements and the time period.

Data center energy monitoring

Systems and methods for resonance aware performance management of processing devices. In one aspect, a method includes iteratively testing a performance operation for the processing device, wherein each iteration is performed at an iteration voltage level for a power delivery network. The performance operation is applied at different application periods and at the iteration voltage level for the iteration. If not failure condition is met, the iteration voltage is reduced and another iteration is done. Upon a failure occurring at a particular application period, an operational voltage level for the power delivery network that is based on the iteration voltage level for the iteration in which a failure condition was induced is selected, and application of the performance operation at the particular application period is precluded.

This disclosure relates to power balancer circuits that enable multiple load zones of an IC to be powered in series while maintaining balanced voltage at each load zone. In one aspect, a circuit includes load zones that are powered in series. The circuit includes a power balancer for balancing a voltage across each load zone. The power balancer includes an equivalent DC transformer array that includes, for each load zone, an equivalent DC transformer connected in parallel with the load zone. The power balancer includes, for each load zone, a bus capacitor connected in parallel with the load zone. Each equivalent DC transformer is electrically connected to each other equivalent DC transformer providing an electrical path for each bus capacitor to discharge current to each other bus capacitor when a voltage across a bus capacitor is greater than a voltage across another bus capacitor.

Power balancer for series-connected load zones of an integrated circuit

An electromagnetic interference ('EMI') sheet attenuator includes a planar conductive layer, a first flexible substrate and a second flexible substrate. The first flexible substrate overlies the metal backing layer and including a conductive pattern on a surface of the first flexible substrate. The second flexible substrate overlies the first flexible substrate and also includes the conductive pattern. The conductive pattern on the second flexible substrate is aligned with the conductive pattern on the first flexible substrate.

Electromagnetic interference ('EMI') sheet attenuators

An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connector of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.

A cooling system, for example, for rack mounted electronic devices (e.g., servers, processors, memory, networking devices or otherwise) in a data center. In various disclosed implementations, the cooling system may be or include a liquid cold plate assembly that is part of or integrated with a server tray package. In some implementations, the liquid cold plate assembly includes a base portion and a top portion that, in combination, form a cooling liquid flow path through which a cooling liquid is circulated and a thermal interface between one or more heat generating devices and the cooling liquid.

Cooling electronic devices in a data center

The systems and methods described are for adjusting over current protection values during changes in load current. In one aspect, a method includes, monitoring a load current amplitude value at a power input connected to an electrical load; determining a rate of change of the load current amplitude value; determining whether the rate of change of the load current amplitude value exceeds a predefined rate threshold value; in response to determining that the rate of change of the load current amplitude value exceeds the predefined rate threshold value: adjusting an over current protection value from a first over current protection value to an adjusted over current protection value for a first predefined amount of time; and at the expiration of the first predefined amount of time, at least partially reversing the adjustment to the over current protection value.

Adjusting over current protection values during changes in load current

An IC package is configured to receive a voltage regulator and a load. The IC package includes a plurality of buildup layers disposed on a plurality of core layers. The buildup layers have a top side that includes first and second surface features for receiving the voltage regulator and the load, respectively. First and second pluralities of vias connect the first and second surface features, respectively, to a buildup conductor layer and a core conductor layer. The buildup conductor layer includes a substantially solid or continuous conductor plane extending across and connected to the first and second pluralities of vias. The buildup conductor layer defines a gap between the first and second pluralities of vias, the gap partially separating a portion of the conductor plane connected to the first plurality of vias from a portion connected to the second plurality of vias.

Protective barrier for integrated circuit packages housing a voltage regulator and a load

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for identifying, for each of multiple circuits of an electrical device, a discharge time that indicates an amount of time previously taken for a voltage level of the circuit to decrease from a normal operating voltage to a specified voltage level after power was removed from the circuit. A delay time period is determined for the electrical device based on each discharge time. A command is received to cycle power to one or more components of the electrical device. In response to receiving the command, power is removed from the circuits for an amount of time that corresponds to the delay time period and power is restored to the circuits in response to the amount of time lapsing.

Growing community of inventors

Sunnyvale, CA, United States of America

Gregory Sizikov