Hewlett-packard Company

Intel Corporation

Gregory S Averill

Ganesh Kumar

Dheemanth Nagaraj

Vincent R Freytag

Eric R Delano

Eric R DeLano

Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are also disclosed.

Memory mirroring and migration at home agent

In one embodiment, a method includes receiving a read request from a first caching agent and if a directory entry associated with the request is in an unknown state, an invalidating snoop message is sent to at least one other caching agent to invalidate information in a cache location of the other caching agent corresponding to the location of the read request, to enable setting of the directory entry into a known state. Other embodiments are described and claimed.

Controllably exiting an unknown state of a cache coherency directory

Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.

Home agent data and memory management

A system and method for testing and verifying the correctness of cache accesses on a model or implementation of a processor that performs speculative and or out-of-order instruction execution. For each behavioral model of a processor under test in a simulation system, an architectural model is created that is fed the same instruction stream and system bus stimulus. The architectural model is capable of correctly and independently executing the instruction stream. The cache and TLB state of the architectural model are kept synchronous with those of the behavioral model under test. Cache synchronization is achieved by reporting, matching and verifying all speculative cache activity and all out-of-order cache accesses, move-ins and move-outs by the behavioral model as it occurs rather than in natural program order.

Verification of accesses in a functional model of a speculative

A system and method for verifying the correct behavior of instruction and data fetches and the order of instruction and data fetch resource modifications by a speculative and or out-of-order computer architecture under test is presented. An architectural model which models the high-level architectural requirements of the computer architecture under test, including instruction fetch resources and data fetch resources, executes test stimuli instructions in natural program order. A behavioral model, which models the high-level architectural requirements of the computer architecture, including instruction fetch resources and data fetch resources, executes the same test stimuli instructions, but according to the speculative and or out-of-order instruction execution behavior defined by the computer architecture under test. Modifications to instruction fetch resources and data fetch resources by the behavioral model are respectively recorded separately in a respective instruction fetch resource event queue and data fetch resource event queue. Upon detection of a fetch instruction event by the behavioral model, each instruction fetch resource event stored in the instruction fetch resource event queue which has a corresponding timestamp earlier than the timestamp of the detected fetch instruction event is applied to the architectural model in timestamp order. Separately, upon detection of a data access request event by the behavioral model, each data fetch resource event stored in the data fetch resource event queue which has a corresponding timestamp earlier than the timestamp of the detected data access event is applied to the architectural model in timestamp order.

Verification of instruction and data fetch resources in a functional

A system and method for detecting architectural violations of strongly ordered instructions by a computer architecture under test that supports out-of-order instruction execution is presented. A synchronizer concurrently controls the execution of an architectural model, which models high-level architectural requirements of the computer architecture under test and generates correct results under all received instruction test stimuli, and a behavioral model, which models the high-level architectural requirements of the computer architecture under test and executes instruction test stimuli according to the out-f-order instruction execution behavior defined by the computer architecture. The synchronizer matches all out-of-order instruction execution effects. The synchronizer verifies the correct handling of strongly ordered instruction by the computer architecture under test by keeping track of coherency check addresses from the bus emulator to the behavioral model, each memory request issued by the behavioral model to the bus emulator for any memory address other than the coherency check address, each respective move-in of a copy of each memory address, each access of each of the logged memory addresses, and each access of each logged coherency check address. If between the issuance of a coherency check on a coherency check address and a subsequent access of the same coherency check address without a new move-in of the coherency check address, the behavioral model moves in a copy of a memory address and accesses that copy, an architectural violation in handling strongly ordered instructions by the computer architecture under test is indicated.

Verification of strongly ordered memory accesses in a functional model

A system and method for using N unidirectional lines to implement signals for arbitration, variable length transactions, automatic responses, and efficient burst transaction modes for a bus in a cache-coherent multi-processor computer system having N processors. Processors use arbitration lines to implement busy signals for variable length transactions. A processor needing to respond to a transaction is granted automatic access to a bus if it is the last processor asserting a busy signal. A processor in a burst transaction mode is granted automatic continuous access without arbitration if no other processors request access. The use of only N lines minimizes pin-out for an integrated processor. The use of unidirectional (one driver, N-1 receivers) lines further optimizes cost and speed.

Growing community of inventors

Fort Collins, CO, United States of America

Gregory S Averill