Texas Instruments Corporation

Texas Instruments France

Gregory Remy Philippe Conti

Narendar M Shankar

Aymeric S Vial

Mehdi-Laurent Akkar

Steven C Goss

Jerome Laurent Azema

Jerome Neanne

Jerome Laurent Azema Le Cellini

Steven Charles c/o Texas Instruments France Goss

A secure demand paging system () includes a processor () operable for executing instructions, an internal memory () for a first page in a first virtual machine context, an external memory () for a second page in a second virtual machine context, and a security circuit () coupled to the processor () and to the internal memory () for maintaining the first page secure in the internal memory (). The processor () is operable to execute sets of instructions representing: a central controller (), an abort handler () coupled to supply to the central controller () at least one signal representing a page fault by an instruction in the processor (), a scavenger () responsive to the central controller () and operable to identify the first page as a page to free, a virtual machine context switcher () responsive to the central controller () to change from the first virtual machine context to the second virtual machine context; and a swapper manager () operable to swap in the second page from the external memory () with decryption and integrity check, to the internal memory () in place of the first page.

Methods, apparatus, and systems for secure demand paging and paging operations for processor devices

A method and system of verifying proper execution of a secure mode entry sequence. At least some of the exemplary embodiments may be a method comprising delivering an instruction from a memory to a processor across an instruction bus (the instruction at least partially configures the processor for secure mode of operation different that privilege modes of the processor), verifying delivery of the instruction across the instruction bus, and checking for proper execution of the instruction using a trace port of the processor.

Monitoring circuit for allowing a processor to enter secure mode upon confirming proper execution of a non-speculative instruction

A secure demand paging system including a secure internal memory, an external non-volatile memory having encrypted and integrity-protected code pages, an external volatile memory for swap pages and a processor coupled to said secure internal memory and to said external non-volatile memory and operable to decrypt and verify the integrity of the code pages thereby to transfer code pages to said secure internal memory directly from said external non-volatile memory bypassing said external volatile memory in respect of the code pages, and to swap out and swap in the swap pages between secure internal memory and said external volatile memory bypassing said external non-volatile memory in respect of the swap pages for said external volatile memory.

Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices

A secure demand paging system includes a secure internal memory having a table relating physical addresses to virtual addresses, a non-volatile memory, a decryption module and a hash module between the secure memory and the non-volatile memory to allow for decryption and integrity verification of data stored in the non-volatile memory during a transfer to said secure memory and means for connecting the secure memory to a volatile page swap memory such that the non-volatile memory is bypassable during a page swap.

A secure demand paging system includes a processor operable for executing instructions, an internal memory for a first page in a first virtual machine context, an external memory for a second page in a second virtual machine context, and a security circuit coupled to the processor and to the internal memory for maintaining the first page secure in the internal memory. The processor is operable to execute sets of instructions representing: a central controller, an abort handler coupled to supply to the central controller at least one signal representing a page fault by an instruction in the processor, a scavenger responsive to the central controller and operable to identify the first page as a page to free, a virtual machine context switcher responsive to the central controller to change from the first virtual machine context to the second virtual machine context; and a swapper manager operable to swap in the second page from the external memory with decryption and integrity check, to the internal memory in place of the first page.

A computing system comprising a processor having a first and second bus (the processor on a first semiconductor die mounted within a semiconductor package), a monitoring device coupled to both the first and second bus of the processor (the monitoring device on the first semiconductor die mounted within the semiconductor package), a memory coupled to the processor via the first bus (coupled to the monitoring device via a security signal, the memory on a second semiconductor die mounted within the semiconductor package), and a user interface external of the semiconductor package (the user interface coupled to the processor via the second data and instruction bus). The monitoring device checks one or both of the first and second busses to determine whether a secure mode entry sequence is delivered to the processor. The first bus and the security signal are only coupled to and accessible by devices within the semiconductor package.

System and method for secure mode for processors and memories on multiple semiconductor dies within a single semiconductor package

State machine for monitoring a trace port and verifying proper execution of a secure mode entry sequence instruction

A system and method of identifying and preventing security violations within a computing system. Some exemplary embodiments may be a method comprising monitoring activity on a core bus coupled to a processor core (the processor core operating in a computing system), identifying activity on the core bus as a security violation, and preventing execution of an instruction within the processor core in response to the security violation.

System and method of identifying and preventing security violations within a computing system

A system and method for detecting a security violation using an error correction code. Some illustrative embodiments may be a method used in a computing system comprising reading a codeword comprising data and an error correction code (ECC) (the ECC associated with the data), deriving an error location polynomial (ELP) from the codeword, determining a total number of codeword errors from the ELP, and preventing access to the data within the codeword if the total number of codeword errors exceeds a maximum number of correctable errors.

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Saint Paul, France

Gregory Remy Philippe Conti